(In reply to comment #14)
> (In reply to comment #13)
> > Do the PLL values in the log files I posted indicate a problem, or are they
> > okay?
> 
> [drm:radeon_compute_pll_avivo], 14875, pll dividers - fb: 23.8 ref: 2, post 8
> [drm:radeon_compute_pll_avivo], 7406, pll dividers - fb: 23.7 ref: 2, post 16
> 
> The display pll looks fine to me. The clock formula is:
> 
> pixel_clock = (reference_frequency * feedback_divider) / (reference_divider
> * post_divider)
> 
> The reference frequency is 100 Mhz, so:
> 
> (100Mhz * 23.8) / (2 * 8) = 148.75Mhz
> 
> (100Mhz * 23.7) / (2 * 16) = 74.0625Mhz
> 
> > 
> > How can you see the PLL values fglrx is using?
> 
> You'd need to dump the PLL registers using radeonreg
> (http://cgit.freedesktop.org/~airlied/radeontool/).
> PPLL1
> 0x400 - ref div - bits 9:0
> 0x404 - fb div - whole part bits 26:16, fractional part bits 3:0
> 0x408 - post div - bits 6:0
> PPLL2
> 0x440 - ref div - bits 9:0
> 0x444 - fb div - whole part bits 26:16, fractional part bits 3:0
> 0x448 - post div - bits 6:0
> 
> e.g., ./radeonreg regmatch 0x400

I got the results with fglrx:
PPLL1@50Hz:     fb=23.7    ref=2    post=6
PPLL2@50Hz:     fb=296.16  ref=7    post=6
PPLL1@23.976Hz: fb=23.7    ref=2    post=12
PPLL2@23.976Hz: fb=296.16  ref=7    post=6

PPLL2 does seem to be used as it does not change. PPLL1 has different values
than with the radeon OSS driver. What does this mean?