New DSI IP has shadow register and working reg. The register values are writen to shadow register. And then trigger with commit reg, the register values will be moved working register.
This fucntion is defualt on. But this driver doesn't use this function. So add the disable control.
Signed-off-by: Jitao Shi jitao.shi@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index ac8e80e379f7..314bfb1c827b 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -123,6 +123,10 @@ #define VM_CMD_EN BIT(0) #define TS_VFP_EN BIT(5)
+#define DSI_SHADOW_DEBUG 0x190U +#define FORCE_COMMIT BIT(0) +#define BYPASS_SHADOW BIT(1) + #define CONFIG (0xff << 0) #define SHORT_PACKET 0 #define LONG_PACKET 2 @@ -149,6 +153,7 @@ struct phy;
struct mtk_dsi_driver_data { const u32 reg_cmdq_off; + bool has_shadow_ctl; };
struct mtk_dsi { @@ -586,6 +591,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) }
mtk_dsi_enable(dsi); + + if (dsi->driver_data->has_shadow_ctl) + writel(FORCE_COMMIT | BYPASS_SHADOW, + dsi->regs + DSI_SHADOW_DEBUG); + mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi);