On Wed, 2021-09-15 at 09:57 +0100, Melissa Wen wrote:
On 09/14, Iago Toral Quiroga wrote:
The hardware sets the TMUWCF bit back to 0 when the TMU write combiner flush completes so we should be checking for that instead of the L2TFLS bit.
Fixes spurious Vulkan CTS failures in: dEQP-VK.binding_model.descriptorset_random.*
Hi Iago,
makes sense to me.
can you add the fix tag? Fixes: d223f98f02099 ("drm/v3d: Add support for compute shader dispatch")
also, you forgot to add your Signed-off-by tag.
Will include both, thanks.
drivers/gpu/drm/v3d/v3d_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c index a3529809d547..5159f544bc16 100644 --- a/drivers/gpu/drm/v3d/v3d_gem.c +++ b/drivers/gpu/drm/v3d/v3d_gem.c @@ -197,7 +197,7 @@ v3d_clean_caches(struct v3d_dev *v3d)
V3D_CORE_WRITE(core, V3D_CTL_L2TCACTL, V3D_L2TCACTL_TMUWCF); if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
V3D_L2TCACTL_L2TFLS), 100)) {
V3D_L2TCACTL_TMUWCF), 100)) {flush\n");
hm.. would it be clearer to say "TMU write combiner" here?
Yes, I guess it does. I'll add this too.
in the next version, you can already include: Reviewed-by: Melissa Wen mwen@igalia.com
Thanks!
Iago
Thanks,
Melissa
}
-- 2.25.1