-Avoidded duplicate logic for the timing calculations -Removed func ade_set_pix_clk and combined it with func ade_ldi_set_mode
Signed-off-by: Satendra Singh Thakur satendra.t@samsung.com Cc: Madhur Verma madhur.verma@samsung.com Cc: Hemanshu Srivastava hemanshu.s@samsung.com --- drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c | 42 ++++++++++---------- drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 52 +++++++++---------------- 2 files changed, 39 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c index b4c7af3..902f63f 100644 --- a/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c +++ b/drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c @@ -23,6 +23,7 @@ #include <drm/drm_mipi_dsi.h> #include <drm/drm_encoder_slave.h> #include <drm/drm_atomic_helper.h> +#include <video/videomode.h>
#include "dw_dsi_reg.h"
@@ -447,7 +448,7 @@ static void dsi_set_mode_timing(void __iomem *base, struct drm_display_mode *mode, enum mipi_dsi_pixel_format format) { - u32 hfp, hbp, hsw, vfp, vbp, vsw; + struct videomode vm; u32 hline_time; u32 hsa_time; u32 hbp_time; @@ -467,25 +468,22 @@ static void dsi_set_mode_timing(void __iomem *base, * The DSI IP accepts vertical timing using lines as normal, * but horizontal timing is a mixture of pixel-clocks for the * active region and byte-lane clocks for the blanking-related - * timings. hfp is specified as the total hline_time in byte- - * lane clocks minus hsa, hbp and active. + * timings. vm.hfront_porch is specified as the total hline_time + * in byte-lane clocks minus hsa, vm.hback_porch and active. */ pixel_clk_kHz = mode->clock; htot = mode->htotal; vtot = mode->vtotal; - hfp = mode->hsync_start - mode->hdisplay; - hbp = mode->htotal - mode->hsync_end; - hsw = mode->hsync_end - mode->hsync_start; - vfp = mode->vsync_start - mode->vdisplay; - vbp = mode->vtotal - mode->vsync_end; - vsw = mode->vsync_end - mode->vsync_start; - if (vsw > 15) { - DRM_DEBUG_DRIVER("vsw exceeded 15\n"); - vsw = 15; + + drm_display_mode_to_videomode(mode, &vm); + + if (vm.vsync_len > 15) { + DRM_DEBUG_DRIVER("vm.vsync_len exceeded 15\n"); + vm.vsync_len = 15; }
- hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz; - hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz; + hsa_time = (vm.hsync_len * lane_byte_clk_kHz) / pixel_clk_kHz; + hbp_time = (vm.hback_porch * lane_byte_clk_kHz) / pixel_clk_kHz; tmp = (u64)htot * (u64)lane_byte_clk_kHz; hline_time = DIV_ROUND_UP(tmp, pixel_clk_kHz);
@@ -494,17 +492,17 @@ static void dsi_set_mode_timing(void __iomem *base, writel(hbp_time, base + VID_HBP_TIME); writel(hline_time, base + VID_HLINE_TIME);
- writel(vsw, base + VID_VSA_LINES); - writel(vbp, base + VID_VBP_LINES); - writel(vfp, base + VID_VFP_LINES); + writel(vm.vsync_len, base + VID_VSA_LINES); + writel(vm.vback_porch, base + VID_VBP_LINES); + writel(vm.vfront_porch, base + VID_VFP_LINES); writel(mode->vdisplay, base + VID_VACTIVE_LINES); writel(mode->hdisplay, base + VID_PKT_SIZE);
- DRM_DEBUG_DRIVER("htot=%d, hfp=%d, hbp=%d, hsw=%d\n", - htot, hfp, hbp, hsw); - DRM_DEBUG_DRIVER("vtol=%d, vfp=%d, vbp=%d, vsw=%d\n", - vtot, vfp, vbp, vsw); - DRM_DEBUG_DRIVER("hsa_time=%d, hbp_time=%d, hline_time=%d\n", + DRM_DEBUG_DRIVER("htot=%d, vm.hfront_porch=%d, vm.hback_porch=%d, vm.hsync_len=%d\n", + htot, vm.hfront_porch, vm.hback_porch, vm.hsync_len); + DRM_DEBUG_DRIVER("vtol=%d, vm.vfront_porch=%d, vm.vback_porch=%d, vm.vsync_len=%d\n", + vtot, vm.vfront_porch, vm.vback_porch, vm.vsync_len); + DRM_DEBUG_DRIVER("hsa_time=%d, vm.hback_porch_time=%d, hline_time=%d\n", hsa_time, hbp_time, hline_time); }
diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c index 2269be9..c3eea17 100644 --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c @@ -30,6 +30,7 @@ #include <drm/drm_plane_helper.h> #include <drm/drm_gem_cma_helper.h> #include <drm/drm_fb_cma_helper.h> +#include <video/videomode.h>
#include "kirin_drm_drv.h" #include "kirin_ade_reg.h" @@ -190,24 +191,6 @@ static bool ade_crtc_mode_fixup(struct drm_crtc *crtc, return true; }
- -static void ade_set_pix_clk(struct ade_hw_ctx *ctx, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - u32 clk_Hz = mode->clock * 1000; - int ret; - - /* - * Success should be guaranteed in mode_valid call back, - * so failure shouldn't happen here - */ - ret = clk_set_rate(ctx->ade_pix_clk, clk_Hz); - if (ret) - DRM_ERROR("failed to set pixel clk %dHz (%d)\n", clk_Hz, ret); - adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000; -} - static void ade_ldi_set_mode(struct ade_crtc *acrtc, struct drm_display_mode *mode, struct drm_display_mode *adj_mode) @@ -216,28 +199,24 @@ static void ade_ldi_set_mode(struct ade_crtc *acrtc, void __iomem *base = ctx->base; u32 width = mode->hdisplay; u32 height = mode->vdisplay; - u32 hfp, hbp, hsw, vfp, vbp, vsw; + struct videomode vm; u32 plr_flags; + int ret;
plr_flags = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? FLAG_NVSYNC : 0; plr_flags |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? FLAG_NHSYNC : 0; - hfp = mode->hsync_start - mode->hdisplay; - hbp = mode->htotal - mode->hsync_end; - hsw = mode->hsync_end - mode->hsync_start; - vfp = mode->vsync_start - mode->vdisplay; - vbp = mode->vtotal - mode->vsync_end; - vsw = mode->vsync_end - mode->vsync_start; - if (vsw > 15) { - DRM_DEBUG_DRIVER("vsw exceeded 15\n"); - vsw = 15; + drm_display_mode_to_videomode(mode, &vm); + if (vm.vsync_len > 15) { + DRM_DEBUG_DRIVER("vm.vsync_len exceeded 15\n"); + vm.vsync_len = 15; }
- writel((hbp << HBP_OFST) | hfp, base + LDI_HRZ_CTRL0); + writel((vm.hback_porch << HBP_OFST) | vm.hfront_porch, + base + LDI_HRZ_CTRL0); /* the configured value is actual value - 1 */ - writel(hsw - 1, base + LDI_HRZ_CTRL1); - writel((vbp << VBP_OFST) | vfp, base + LDI_VRT_CTRL0); + writel(vm.hsync_len - 1, base + LDI_HRZ_CTRL1); + writel((vm.vback_porch << VBP_OFST) | vm.vfront_porch, + base + LDI_VRT_CTRL0); /* the configured value is actual value - 1 */ - writel(vsw - 1, base + LDI_VRT_CTRL1); + writel(vm.vsync_len - 1, base + LDI_VRT_CTRL1); /* the configured value is actual value - 1 */ writel(((height - 1) << VSIZE_OFST) | (width - 1), base + LDI_DSP_SIZE); @@ -253,7 +232,14 @@ static void ade_ldi_set_mode(struct ade_crtc *acrtc, writel(width * height - 1, base + ADE_CTRAN_IMAGE_SIZE(ADE_CTRAN6)); ade_update_reload_bit(base, CTRAN_OFST + ADE_CTRAN6, 0);
- ade_set_pix_clk(ctx, mode, adj_mode); + /* + * Success should be guaranteed in mode_valid call back, + * so failure shouldn't happen here + */ + ret = clk_set_rate(ctx->ade_pix_clk, vm.pixelclock); + if (ret) + DRM_ERROR("failed to set pixel clk %dHz (%d)\n", + vm.pixelclock, ret); + adj_mode->clock = clk_get_rate(ctx->ade_pix_clk) / 1000;
DRM_DEBUG_DRIVER("set mode: %dx%d\n", width, height); }