On Tue, Sep 18, 2018 at 12:04:35PM -0700, Manasi Navare wrote:
Thanks Imre for your review comments. Please find the comments below:
On Fri, Sep 14, 2018 at 01:55:00PM +0300, Imre Deak wrote:
On Tue, Sep 11, 2018 at 05:56:01PM -0700, Manasi Navare wrote:
On Icelake, a separate power well PG2 is created for VDSC engine used for eDP/MIPI DSI. This patch adds a new display power domain for Power well 2.
Cc: Rodrigo Vivi rodrigo.vivi@intel.com Cc: Imre Deak imre.deak@intel.com Signed-off-by: Manasi Navare manasi.d.navare@intel.com
drivers/gpu/drm/i915/intel_display.h | 1 + drivers/gpu/drm/i915/intel_runtime_pm.c | 12 ++++++------ 2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h index 3fe52788b4cf..bef71d27cdfe 100644 --- a/drivers/gpu/drm/i915/intel_display.h +++ b/drivers/gpu/drm/i915/intel_display.h @@ -256,6 +256,7 @@ enum intel_display_power_domain { POWER_DOMAIN_MODESET, POWER_DOMAIN_GT_IRQ, POWER_DOMAIN_INIT,
- POWER_DOMAIN_VDSC_EDP_MIPI,
This is better named VDSC_PIPE_A. The other pipes have also VDSC functionality which could be on separate power wells in the future.
Yea naming it as VDSC_PIPE_A makes sense since eDP/MIPI DSI on Pipe A will use this VDSC power well. I will change this in the next revision.
Isn't the VDSC in the transcoder for now though? And I guess it's moving to the pipe later?
If we call it PIPE_A then it's going to a bit confusing when we use it with pipe B or C. Needs at least clear comments in the code why we're doing something that looks like nonsense of the first glance.