On Tue, 2022-04-12 at 15:43 +0800, Rex-BC Chen wrote:
On Mon, 2022-04-11 at 11:07 +0200, AngeloGioacchino Del Regno wrote:
Il 11/04/22 04:31, xinlei.lee@mediatek.com ha scritto:
From: Jitao Shi jitao.shi@mediatek.com
To comply with the panel sequence, hold the mipi signal to LP00 before the dcs cmds transmission, and pull the mipi signal high from LP00 to LP11 until the start of the dcs cmds transmission. The normal panel timing is : (1) pp1800 DC pull up (2) avdd & avee AC pull high (3) lcm_reset pull high -> pull low -> pull high (4) Pull MIPI signal high (LP11) -> initial code -> send video data(HS mode) The power-off sequence is reversed. If dsi is not in cmd mode, then dsi will pull the mipi signal high in the mtk_output_dsi_enable function.
Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API")
Signed-off-by: Jitao Shi jitao.shi@mediatek.com Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com
drivers/gpu/drm/mediatek/mtk_dsi.c | 28 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index cf76c53a1af6..9ad6f08c8bfe 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -203,6 +203,7 @@ struct mtk_dsi { struct mtk_phy_timing phy_timing; int refcount; bool enabled;
- bool lanes_ready; u32 irq_data; wait_queue_head_t irq_wait_queue; const struct mtk_dsi_driver_data *driver_data;
@@ -654,13 +655,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi);
- mtk_dsi_rxtx_control(dsi);
- usleep_range(30, 100);
- mtk_dsi_reset_dphy(dsi);
- mtk_dsi_clk_ulp_mode_leave(dsi);
- mtk_dsi_lane0_ulp_mode_leave(dsi);
- mtk_dsi_clk_hs_mode(dsi, 0);
- return 0; err_disable_engine_clk: clk_disable_unprepare(dsi->engine_clk);
@@ -689,6 +683,23 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) clk_disable_unprepare(dsi->digital_clk);
phy_power_off(dsi->phy);
- dsi->lanes_ready = false;
+}
+static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) +{
- if (!dsi->lanes_ready) {
dsi->lanes_ready = true;mtk_dsi_rxtx_control(dsi);usleep_range(30, 100);mtk_dsi_reset_dphy(dsi);mtk_dsi_clk_ulp_mode_leave(dsi);mtk_dsi_lane0_ulp_mode_leave(dsi);mtk_dsi_clk_hs_mode(dsi, 0);msleep(20);This is a very long sleep, which wasn't present before this change. Please document the reasons why we need this 20ms sleep with a comment in the code.
Regards, Angelo
Hello Xinlei,
As Angelo mentioned. I think you should add this in commit message and driver comments. (Your reply in v3.) "The 20ms delay in mtk_dsi_lane_ready() is because dsi needs to give dsi_rx(panel) a reaction time after pulling up the mipi signal."
BRs, Rex
Hey Rex:
Thanks for your review and reminder. I will add this explanation in the next edition of code & comments.
Best Regards! xinlei