tree: git://people.freedesktop.org/~agd5f/linux.git amd-staging-drm-next head: b52e33cc86142a1143ed41806d9caf631cf16b21 commit: d78fd342a085cbce6b7919651d1005e44dc0d973 [875/881] drm/amd/powerplay: remove unused parameter of phm_start_thermal_controller config: x86_64-allmodconfig (attached as .config) compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025 reproduce: git checkout d78fd342a085cbce6b7919651d1005e44dc0d973 # save the attached .config to linux build tree make ARCH=x86_64
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:45: sparse: bogus scalar initializer drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c: In function 'phm_start_thermal_controller':
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:9: warning: braces around scalar initializer
struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, TEMP_RANGE_MAX}}; ^~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:9: note: (near initialization for 'range.min')
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:31:24: warning: excess elements in scalar initializer
#define TEMP_RANGE_MAX (80 * 1000) ^
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:55: note: in expansion of macro 'TEMP_RANGE_MAX'
struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, TEMP_RANGE_MAX}}; ^~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:31:24: note: (near initialization for 'range.min') #define TEMP_RANGE_MAX (80 * 1000) ^
drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c:230:55: note: in expansion of macro 'TEMP_RANGE_MAX'
struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, TEMP_RANGE_MAX}}; ^~~~~~~~~~~~~~
sparse warnings: (new ones prefixed by >>)
vim +/TEMP_RANGE_MAX +230 drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/hardwaremanager.c
28 29 30 #define TEMP_RANGE_MIN (0)
31 #define TEMP_RANGE_MAX (80 * 1000)
32 33 #define PHM_FUNC_CHECK(hw) \ 34 do { \ 35 if ((hw) == NULL || (hw)->hwmgr_func == NULL) \ 36 return -EINVAL; \ 37 } while (0) 38 39 int phm_setup_asic(struct pp_hwmgr *hwmgr) 40 { 41 PHM_FUNC_CHECK(hwmgr); 42 43 if (NULL != hwmgr->hwmgr_func->asic_setup) 44 return hwmgr->hwmgr_func->asic_setup(hwmgr); 45 46 return 0; 47 } 48 49 int phm_power_down_asic(struct pp_hwmgr *hwmgr) 50 { 51 PHM_FUNC_CHECK(hwmgr); 52 53 if (NULL != hwmgr->hwmgr_func->power_off_asic) 54 return hwmgr->hwmgr_func->power_off_asic(hwmgr); 55 56 return 0; 57 } 58 59 int phm_set_power_state(struct pp_hwmgr *hwmgr, 60 const struct pp_hw_power_state *pcurrent_state, 61 const struct pp_hw_power_state *pnew_power_state) 62 { 63 struct phm_set_power_state_input states; 64 65 PHM_FUNC_CHECK(hwmgr); 66 67 states.pcurrent_state = pcurrent_state; 68 states.pnew_state = pnew_power_state; 69 70 if (NULL != hwmgr->hwmgr_func->power_state_set) 71 return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); 72 73 return 0; 74 } 75 76 int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) 77 { 78 int ret = 1; 79 bool enabled; 80 PHM_FUNC_CHECK(hwmgr); 81 82 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) 83 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); 84 85 enabled = ret == 0; 86 87 cgs_notify_dpm_enabled(hwmgr->device, enabled); 88 89 return ret; 90 } 91 92 int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr) 93 { 94 int ret = -1; 95 bool enabled; 96 97 PHM_FUNC_CHECK(hwmgr); 98 99 if (hwmgr->hwmgr_func->dynamic_state_management_disable) 100 ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); 101 102 enabled = ret == 0 ? false : true; 103 104 cgs_notify_dpm_enabled(hwmgr->device, enabled); 105 106 return ret; 107 } 108 109 int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) 110 { 111 int ret = 0; 112 113 PHM_FUNC_CHECK(hwmgr); 114 115 if (hwmgr->hwmgr_func->force_dpm_level != NULL) 116 ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); 117 118 return ret; 119 } 120 121 int phm_reset_power_profile_state(struct pp_hwmgr *hwmgr) 122 { 123 int ret = 0; 124 125 if (hwmgr->hwmgr_func->set_power_profile_state) { 126 if (hwmgr->current_power_profile == AMD_PP_GFX_PROFILE) 127 ret = hwmgr->hwmgr_func->set_power_profile_state( 128 hwmgr, 129 &hwmgr->gfx_power_profile); 130 else if (hwmgr->current_power_profile == AMD_PP_COMPUTE_PROFILE) 131 ret = hwmgr->hwmgr_func->set_power_profile_state( 132 hwmgr, 133 &hwmgr->compute_power_profile); 134 } 135 return ret; 136 } 137 138 int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 139 struct pp_power_state *adjusted_ps, 140 const struct pp_power_state *current_ps) 141 { 142 PHM_FUNC_CHECK(hwmgr); 143 144 if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL) 145 return hwmgr->hwmgr_func->apply_state_adjust_rules( 146 hwmgr, 147 adjusted_ps, 148 current_ps); 149 return 0; 150 } 151 152 int phm_powerdown_uvd(struct pp_hwmgr *hwmgr) 153 { 154 PHM_FUNC_CHECK(hwmgr); 155 156 if (hwmgr->hwmgr_func->powerdown_uvd != NULL) 157 return hwmgr->hwmgr_func->powerdown_uvd(hwmgr); 158 return 0; 159 } 160 161 int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr) 162 { 163 PHM_FUNC_CHECK(hwmgr); 164 165 if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) 166 return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); 167 168 return 0; 169 } 170 171 int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr) 172 { 173 PHM_FUNC_CHECK(hwmgr); 174 175 if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) 176 return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); 177 178 return 0; 179 } 180 181 182 int phm_display_configuration_changed(struct pp_hwmgr *hwmgr) 183 { 184 PHM_FUNC_CHECK(hwmgr); 185 186 if (NULL != hwmgr->hwmgr_func->display_config_changed) 187 hwmgr->hwmgr_func->display_config_changed(hwmgr); 188 189 return 0; 190 } 191 192 int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) 193 { 194 PHM_FUNC_CHECK(hwmgr); 195 196 if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) 197 hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); 198 199 return 0; 200 } 201 202 int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr) 203 { 204 PHM_FUNC_CHECK(hwmgr); 205 206 if (hwmgr->hwmgr_func->stop_thermal_controller == NULL) 207 return -EINVAL; 208 209 return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr); 210 } 211 212 int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info) 213 { 214 PHM_FUNC_CHECK(hwmgr); 215 216 if (hwmgr->hwmgr_func->register_internal_thermal_interrupt != NULL) 217 return hwmgr->hwmgr_func->register_internal_thermal_interrupt(hwmgr, info); 218 219 return 0; 220 } 221 222 /** 223 * Initializes the thermal controller subsystem. 224 * 225 * @param pHwMgr the address of the powerplay hardware manager. 226 * @exception PP_Result_Failed if any of the paramters is NULL, otherwise the return value from the dispatcher. 227 */ 228 int phm_start_thermal_controller(struct pp_hwmgr *hwmgr) 229 {
230 struct PP_TemperatureRange range = {{TEMP_RANGE_MIN, TEMP_RANGE_MAX}};
231 232 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 233 PHM_PlatformCaps_ThermalController) 234 && hwmgr->hwmgr_func->start_thermal_controller != NULL) 235 return hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range); 236 237 return 0; 238 } 239
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