Hi Guido,
Thank you for the patch.
On Wed, Jul 24, 2019 at 05:52:25PM +0200, Guido Günther wrote:
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by: Guido Günther agx@sigxcpu.org
.../bindings/display/bridge/imx-nwl-dsi.txt | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/imx-nwl-dsi.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/imx-nwl-dsi.txt b/Documentation/devicetree/bindings/display/bridge/imx-nwl-dsi.txt new file mode 100644 index 000000000000..288fdb726d5a --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/imx-nwl-dsi.txt @@ -0,0 +1,89 @@ +Northwest Logic MIPI-DSI on imx SoCs +=====================================
There's one too many =.
+NWL MIPI-DSI host controller found on i.MX8 platforms. This is a +dsi bridge for the for the NWL MIPI-DSI host.
s/dsi/DSI/ s/for the for the /for the /
+Required properties: +- compatible: "fsl,<chip>-nwl-dsi"
- The following strings are expected:
"fsl,imx8mq-nwl-dsi"+- reg: the register range of the MIPI-DSI controller +- interrupts: the interrupt number for this module
It's not just a number but a specifier (with flags).
+- clock, clock-names: phandles to the MIPI-DSI clocks
That should be phandles and names.
- The following clocks are expected on all platforms:
Expected or required ?
s/ on all platforms// as you only support a single platform.
"core" - DSI core clock"tx_esc" - TX_ESC clock (used in escape mode)"rx_esc" - RX_ESC clock (used in escape mode)"phy_ref" - PHY_REF clock. Clock is managed by the phy. Onlyused to read the clock rate.+- assigned-clocks: phandles to clocks that require initial configuration +- assigned-clock-rates: rates of the clocks that require initial configuration
- The following clocks need to have an initial configuration:
- "tx_esc" (20 MHz) and "rx_esc" (80 Mhz).
I think those two properties are out of scope for these bindings.
+- phys: phandle to the phy module representing the DPHY
inside the MIPI-DSI IP block+- phy-names: should be "dphy"
+Optional properties: +- power-domains phandle to the power domain +- src phandle to the system reset controller (required on
i.MX8MQ)
Should this use the standard resets property ?
+- mux-sel phandle to the MUX register set (required on i.MX8MQ) +- assigned-clock-parents phandles to parent clocks that needs to be assigned as
parents to clocks defined in assigned-clocks
This property is also out of scope.
+Example:
- mipi_dsi: mipi_dsi@30a00000 {
#address-cells = <1>;#size-cells = <0>;compatible = "fsl,imx8mq-nwl-dsi";reg = <0x30A00000 0x300>;clocks = <&clk IMX8MQ_CLK_DSI_CORE>,<&clk IMX8MQ_CLK_DSI_AHB>,<&clk IMX8MQ_CLK_DSI_IPG_DIV>,<&clk IMX8MQ_CLK_DSI_PHY_REF>;clock-names = "core", "rx_esc", "tx_esc", "phy_ref";assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,<&clk IMX8MQ_CLK_DSI_CORE>,<&clk IMX8MQ_CLK_DSI_IPG_DIV>;assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,<&clk IMX8MQ_SYS1_PLL_266M>;assigned-clock-rates = <80000000>,<266000000>,<20000000>;interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;power-domains = <&pgc_mipi>;src = <&src>;mux-sel = <&iomuxc_gpr>;phys = <&dphy>;phy-names = "dphy";status = "okay";panel@0 {compatible = "...";port {panel_in: endpoint {remote-endpoint = <&mipi_dsi_out>;};};};ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;mipi_dsi_in: endpoint {remote-endpoint = <&dcss_disp0_mipi_dsi>;};};port@1 {reg = <1>;mipi_dsi_out: endpoint {remote-endpoint = <&panel_in>;};};};
The ports should be documented too. There are multiple example bindings available.
- };