(Adding back James again - did you use get_maintainer.pl?)
On Thu, Mar 11, 2021 at 12:08:46PM +0000, carsten.haitzler@foss.arm.com wrote:
From: Carsten Haitzler carsten.haitzler@arm.com
When setting up a readback connector that writes data back to memory rather than to an actual output device (HDMI etc.), rounding was set to round. As the DPU uses a higher internal number of bits when generating a color value, this round-down back to 8bit ended up with everything being off-by one. e.g. #fefefe became #ffffff. This sets
Perhaps overly pedantic, but now we've tracked down what was actually happening I think we can be more precise here. Not _everything_ is off-by-one, it's just rounding in the standard sense - if the most significant bit-to-be-discarded is set, the value is rounded up to minimise the absolute error introduced by bit-depth reduction.
rounding to "round-down" so things end up correct by turning on the LW_TRC round down flag.
Can we call it "truncate" rather than round down? I think it makes "TRC" a bit more understandable.
Signed-off-by: Carsten Haitzler carsten.haitzler@arm.com
drivers/gpu/drm/arm/display/komeda/d71/d71_component.c | 7 ++++++- drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c index 8a02ade369db..e97acc5519d1 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_component.c @@ -468,7 +468,12 @@ static void d71_wb_layer_update(struct komeda_component *c, struct komeda_layer_state *st = to_layer_st(state); struct drm_connector_state *conn_st = state->wb_conn->state; struct komeda_fb *kfb = to_kfb(conn_st->writeback_job->fb);
- u32 ctrl = L_EN | LW_OFM, mask = L_EN | LW_OFM | LW_TBU_EN;
- /* LW_TRC sets rounding to truncate not round which is needed for
* the output of writeback to match the input in the most common* use cases like RGB888 -> RGB888, so set this bit by default*/
Hm, not sure why this file uses "net/" style comments, but as you said, this is in-keeping with the rest of the file, so meh :-)
- u32 ctrl = LW_TRC | L_EN | LW_OFM;
- u32 mask = LW_TRC | L_EN | LW_OFM | LW_TBU_EN;
If you were aiming for matching register order, this should be:
L_EN | LW_TRC | LW_OFM | LW_TBU_EN
I think it'd be nice to have the exact behaviour in the commit message, but either way this seems OK as a pragmatic fix so:
Reviewed-by: Brian Starkey brian.starkey@arm.com
Thanks, -Brian
u32 __iomem *reg = c->reg;
d71_layer_update_fb(c, kfb, st->addr); diff --git a/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h b/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h index e80172a0b320..a8036689d721 100644 --- a/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h +++ b/drivers/gpu/drm/arm/display/komeda/d71/d71_regs.h @@ -321,6 +321,7 @@ #define LAYER_WR_FORMAT 0x0D8
/* Layer_WR control bits */ +#define LW_TRC BIT(1) #define LW_OFM BIT(4) #define LW_LALPHA(x) (((x) & 0xFF) << 8)
#define LW_A_WCACHE(x) (((x) & 0xF) << 28)
2.30.0
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