On Fri, Mar 23, 2018 at 12:49:48PM +0530, Sharat Masetty wrote:
Add client side bindings required for the GPU to use the last level system cache. Also add a register range in the GPU CX domain.
Reviewed-by: Jordan Crouse jcrouse@codeaurora.org
Also, these should go the the devicetree lists for review (but maybe wait until the other changes have gotten further through the process).
Signed-off-by: Sharat Masetty smasetty@codeaurora.org
arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index eb0a1b2..7e2d938 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -887,8 +887,8 @@ compatible = "qcom,adreno-630.2", "qcom,adreno"; #stream-id-cells = <16>;
reg = <0x5000000 0x40000>;reg-names = "kgsl_3d0_reg_memory";
reg = <0x5000000 0x40000>, <0x509e000 0x10>;reg-names = "kgsl_3d0_reg_memory", "cx_mem";/*
- Look ma, no clocks! The GPU clocks and power are controlled
@@ -898,6 +898,10 @@ interrupts = <0 300 0>; interrupt-names = "kgsl_3d0_irq";
/* GPU related llc slices */cache-slice-names = "gpu", "gpuhtw";cache-slices = <&llcc 12>, <&llcc 11>;iommus = <&kgsl_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
-- 1.9.1
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