On 01/31/2015 05:59 AM, Russell King - ARM Linux wrote:
On Fri, Jan 30, 2015 at 06:19:46AM -0500, Yakir Yang wrote:

When transmitting IEC60985 linear PCM audio, we configure the
Aduio Sample Channel Status information of all the channel
status bits in the IEC60958 frame.

It appears that the iMX6 version of the DW-HDMI IP does not have these
registers.  These registers are quite possibly only available on IPs
which do not have the built-in AHB DMA, since the channel status bits
are encoded into the samples in memory.

Can you report what identifying information your version of this IP
outputs please?  On iMX6, I get:

dwhdmi-imx 120000.hdmi: Detected HDMI controller 0x13:0xa:0xa0:0xc1

for iMX6Quad, and for iMX6Solo:

dwhdmi-imx 120000.hdmi: Detected HDMI controller 0x13:0x1a:0xa0:0xc1

Thanks.

Further comments below.

Here are the IP version on rk3288:
    dwhdmi-rockchip ff980000.hdmi: Detected HDMI controller 0x20:0xa:0xa0:0xc1

attache the register description:

5.2.5.50 fc_audschnls0 to fc_audschnls8
    When transmitting IEC60958 linear PCM audio, this registers allow to configure the channel status
    information of all the channel status bits in the IEC60958 frame. For the moment this configuration is only
    used when the I2S audio interface, General Purpose Audio (GPA), or AHB audio DMA (AHBAUDDMA)
    interface is active (for S/PDIF interface this information comes from the stream). Information configured is
    the following:
        IEC Copyright indication
        CGMS-A
        PCM audio mode
        Category code
        Source number
        Channel number for first right sample
        Channel number for second right sample
        Channel number for third right sample
        Channel number for fourth right sample
        Channel number for first left sample
        Channel number for second left sample
        Channel number for third left sample
        Channel number for fourth left sample
        Clock accuracy
        Sampling frequency
        Original sampling frequency
        Word length configuration

Thks for you reply, : )

Best Regards.


diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
index 423addc..2ded957 100644
--- a/drivers/gpu/drm/bridge/dw_hdmi.c
+++ b/drivers/gpu/drm/bridge/dw_hdmi.c
@@ -204,6 +204,47 @@ static void hdmi_regenerate_n_cts(struct dw_hdmi *hdmi, unsigned int n,
 	hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 }
 
+static void hdmi_set_schnl(struct dw_hdmi *hdmi)
+{
+	u8 aud_schnl_samplerate;
+
+	switch (hdmi->sample_rate) {
+	case 32000:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_32K;
+		break;
+	case 44100:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1;
+		break;
+	case 48000:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_48K;
+		break;
+	case 88200:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_88K2;
+		break;
+	case 96000:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_96K;
+		break;
+	case 176400:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_176K4;
+		break;
+	case 192000:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_192K;
+		break;
+	case 768000:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_768K;
+		break;
+	default:
+		aud_schnl_samplerate = HDMI_FC_AUDSCHNLS7_SMPRATE_44K1;
+		break;
+	}
+
+	/* set channel status register */
+	hdmi_modb(hdmi, aud_schnl_samplerate,
+		  HDMI_FC_AUDSCHNLS7_SMPRATE_MASK, HDMI_FC_AUDSCHNLS7);
+	hdmi_writeb(hdmi, ((~aud_schnl_samplerate) << 4) | 0x2,
+		    HDMI_FC_AUDSCHNLS8);
+}
+

You should not split patches up like this - this patch introduces a new
static function, which is never used until a subsequent patch.  If this
patch were to be merged, it would introduce a new build warning.

Please ensure that each patch in the series can be applied in sequence
without causing a regression.

Thanks.