Hi,
On Tue, Feb 4, 2020 at 11:02 PM Sharat Masetty smasetty@codeaurora.org wrote:
This patch adds the required dt nodes and properties to enabled A618 GPU.
Signed-off-by: Sharat Masetty smasetty@codeaurora.org
arch/arm64/boot/dts/qcom/sc7180.dtsi | 102 +++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f3fcc5c..63fff15 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1043,6 +1043,108 @@ }; };
gpu: gpu@5000000 {compatible = "qcom,adreno-618.0", "qcom,adreno";#stream-id-cells = <16>;reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,<0 0x05061000 0 0x800>;reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;iommus = <&adreno_smmu 0>;operating-points-v2 = <&gpu_opp_table>;qcom,gmu = <&gmu>;gpu_opp_table: opp-table {compatible = "operating-points-v2";opp-800000000 {opp-hz = /bits/ 64 <800000000>;opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;};opp-650000000 {opp-hz = /bits/ 64 <650000000>;opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;};opp-565000000 {opp-hz = /bits/ 64 <565000000>;opp-level = <RPMH_REGULATOR_LEVEL_NOM>;};opp-430000000 {opp-hz = /bits/ 64 <430000000>;opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;};opp-355000000 {opp-hz = /bits/ 64 <355000000>;opp-level = <RPMH_REGULATOR_LEVEL_SVS>;};opp-267000000 {opp-hz = /bits/ 64 <267000000>;opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;};opp-180000000 {opp-hz = /bits/ 64 <180000000>;opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;};};};adreno_smmu: iommu@5040000 {compatible = "qcom,sc7180-smmu-v2", "qcom,smmu-v2";
As per prior discussion "qcom,sc7180-smmu-v2" needs to be added to the bindings.
reg = <0 0x05040000 0 0x10000>;#iommu-cells = <1>;#global-interrupts = <2>;interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,<&gcc GCC_GPU_CFG_AHB_CLK>,<&gcc GCC_DDRSS_GPU_AXI_CLK>;clock-names = "bus", "iface", "mem_iface_clk";
As per discussion in v3 [1], "mem_iface_clk" is new and needs to be added to the bindings. Presumably that patch should be posted / Acked by Rob before we land this dts.
Other than relying on un-posted bindings, this looks sane to me and this patch lets me bring the GPU up on my sc7180-based board.
Reviewed-by: Douglas Anderson dianders@chromium.org Tested-by: Douglas Anderson dianders@chromium.org
-Doug
[1] https://lore.kernel.org/r/1e29097cc1cdf18671379f6420f872b0@codeaurora.org