On Mon, May 19, 2014 at 5:33 PM, Thierry Reding thierry.reding@gmail.com wrote:
On Mon, May 19, 2014 at 04:10:56PM +0900, Alexandre Courbot wrote:
From: Lucas Stach dev@lynxeye.de
On arches with non-coherent PCI,
I guess since this applies to gk20a
we need to flush caches ourselfes at
"ourselves". Or perhaps even reword to something like: "..., caches need to be flushed and invalidated explicitly", since dma_sync_for_cpu() does invalidate rather than flush.
Rephrased as "On arches for which access to GPU memory is non-coherent, caches need to be flushed and invalidated explicitly at the appropriate places."
the appropriate places. Introduce two small helpers to make things easy for TTM based drivers.
Signed-off-by: Lucas Stach dev@lynxeye.de Signed-off-by: Alexandre Courbot acourbot@nvidia.com
drivers/gpu/drm/ttm/ttm_tt.c | 25 +++++++++++++++++++++++++ include/drm/ttm/ttm_bo_driver.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
[...]
+void ttm_dma_tt_cache_sync_for_device(struct ttm_dma_tt *ttm_dma,
struct device *dev)+{
int i;This should probably be unsigned long to match the type of ttm_dma->ttm.num_pages.
Fixed.
Thanks, Alex.