Re: [PATCH 16/20] drm/msm/a6xx: Add support for per-instance pagetables

Reviewed-by: Akhil P Oommen akhilpo@codeaurora.org

On 8/18/2020 3:31 AM, Rob Clark wrote:

From: Jordan Crouse jcrouse@codeaurora.org

Add support for using per-instance pagetables if all the dependencies are available.

Signed-off-by: Jordan Crouse jcrouse@codeaurora.org Signed-off-by: Rob Clark robdclark@chromium.org

---

drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 63 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/msm_ringbuffer.h | 1 + 3 files changed, 65 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5eabb0109577..d7ad6c78d787 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -81,6 +81,49 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, OUT_RING(ring, upper_32_bits(iova)); }

+static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,

• struct msm_ringbuffer *ring, struct msm_file_private *ctx)
  

+{

• phys_addr_t ttbr;
• u32 asid;
• u64 memptr = rbmemptr(ring, ttbr0);
• if (ctx == a6xx_gpu->cur_ctx)

• return;
  

• if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))

• return;
  

• /* Execute the table update */
• OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
• OUT_RING(ring,

• CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
  

• CP_SMMU_TABLE_UPDATE_1_ASID(asid));
  

• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
• OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
• /*

• * Write the new TTBR0 to the memstore. This is good for debugging.
  

• */
  

• OUT_PKT7(ring, CP_MEM_WRITE, 4);
• OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
• OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
• OUT_RING(ring, lower_32_bits(ttbr));
• OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
• /*

• * And finally, trigger a uche flush to be sure there isn't anything
  

• * lingering in that part of the GPU
  

• */
  

• OUT_PKT7(ring, CP_EVENT_WRITE, 1);
• OUT_RING(ring, 0x31);
• a6xx_gpu->cur_ctx = ctx;

+}

• static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) { unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;

@@ -90,6 +133,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) struct msm_ringbuffer *ring = submit->ring; unsigned int i;

• a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
• get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP_0_LO, rbmemptr_stats(ring, index, cpcycles_start));

@@ -696,6 +741,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu) /* Always come up on rb 0 */ a6xx_gpu->cur_ring = gpu->rb[0];

• a6xx_gpu->cur_ctx = NULL;
• /* Enable the SQE_to start the CP engine */ gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);

@@ -1008,6 +1055,21 @@ static unsigned long a6xx_gpu_busy(struct msm_gpu *gpu) return (unsigned long)busy_time; }

+static struct msm_gem_address_space * +a6xx_create_private_address_space(struct msm_gpu *gpu) +{

• struct msm_gem_address_space *aspace = NULL;
• struct msm_mmu *mmu;
• mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
• if (!IS_ERR(mmu))

• aspace = msm_gem_address_space_create(mmu,
  

• 	"gpu", 0x100000000ULL, 0x1ffffffffULL);
  

• return aspace;

+}

• static const struct adreno_gpu_funcs funcs = { .base = { .get_param = adreno_get_param,

@@ -1031,6 +1093,7 @@ static const struct adreno_gpu_funcs funcs = { .gpu_state_put = a6xx_gpu_state_put, #endif .create_address_space = adreno_iommu_create_address_space,

• .create_private_address_space = a6xx_create_private_address_space,
  

  }, .get_timestamp = a6xx_get_timestamp, };

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 03ba60d5b07f..da22d7549d9b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -19,6 +19,7 @@ struct a6xx_gpu { uint64_t sqe_iova;

struct msm_ringbuffer *cur_ring;

• struct msm_file_private *cur_ctx;

  struct a6xx_gmu gmu; };

diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h index 7764373d0ed2..0987d6bf848c 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.h +++ b/drivers/gpu/drm/msm/msm_ringbuffer.h @@ -31,6 +31,7 @@ struct msm_rbmemptrs { volatile uint32_t fence;

volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];

• volatile u64 ttbr0; };

  struct msm_ringbuffer {