Add the check if source control mode is supported by the PCON, before starting configuring PCON for FRL training, as per spec VESA DP2.0-HDMI2.1 PCON Draft-1 Sec-7.
v2: Added spec details for the change. (Uma)
Signed-off-by: Ankit Nautiyal ankit.k.nautiyal@intel.com Reviewed-by: Uma Shankar uma.shankar@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 00a621d583f6..4fdfd4f06933 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2638,8 +2638,13 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- /* Always go for FRL training if supported */ - if (!intel_dp_is_hdmi_2_1_sink(intel_dp) || + /* + * Always go for FRL training if: + * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) + * -sink is HDMI2.1 + */ + if (!(intel_dp->dpcd[2] & DP_PCON_SOURCE_CTL_MODE) || + !intel_dp_is_hdmi_2_1_sink(intel_dp) || intel_dp->frl.is_trained) return;