the register offset and value will be different in future SOC, add private data for rdma1->dsi0 use case.
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 0015b35..296b157 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -174,6 +174,8 @@ struct mtk_mmsys_reg_data { u32 rdma1_sout_dpi0; u32 dpi0_sel_in; u32 dpi0_sel_in_rdma1; + u32 dsi0_sel_in; + u32 dsi0_sel_in_rdma1; };
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { @@ -256,6 +258,8 @@ struct mtk_mmsys_reg_data {
const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = { .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN, + .dsi0_sel_in = DISP_REG_CONFIG_DSI_SEL, + .dsi0_sel_in_rdma1 = DSI_SEL_IN_RDMA, };
const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data = { @@ -264,6 +268,8 @@ struct mtk_mmsys_reg_data { .rdma1_sout_dpi0 = RDMA1_SOUT_DPI0, .dpi0_sel_in = DISP_REG_CONFIG_DPI_SEL_IN, .dpi0_sel_in_rdma1 = DPI0_SEL_IN_RDMA1, + .dsi0_sel_in = DISP_REG_CONFIG_DSIE_SEL_IN, + .dsi0_sel_in_rdma1 = DSI0_SEL_IN_RDMA1, };
static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data, @@ -363,8 +369,8 @@ static unsigned int mtk_ddp_sel_in(const struct mtk_mmsys_reg_data *data, *addr = DISP_REG_CONFIG_DPI_SEL_IN; value = DPI1_SEL_IN_RDMA1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { - *addr = DISP_REG_CONFIG_DSIE_SEL_IN; - value = DSI0_SEL_IN_RDMA1; + *addr = data->dsi0_sel_in; + value = data->dsi0_sel_in_rdma1; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) { *addr = DISP_REG_CONFIG_DSIO_SEL_IN; value = DSI1_SEL_IN_RDMA1;