Hi Jacopo,
Thank you for the patch.
On Monday, 30 July 2018 20:20:13 EEST Jacopo Mondi wrote:
Rename the 'value' variable, only used to for writing to DMSR register to a more precise 'dmsr' name.
Signed-off-by: Laurent Pinchart laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Jacopo Mondi jacopo@jmondi.org
I think this simple change can be squashed with patch 1/3.
drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c index 6d55cec..4d7907c 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c @@ -208,7 +208,7 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; struct rcar_du_device *rcdu = rcrtc->group->dev; unsigned long mode_clock = mode->clock * 1000;
- u32 value;
u32 dsmr; u32 escr;
if (rcdu->info->dpll_ch & (1 << rcrtc->index)) {
@@ -299,11 +299,11 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc) rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
/* Signal polarities */
- value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
| ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)| ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)| DSMR_DIPM_DISP | DSMR_CSPM;- rcar_du_crtc_write(rcrtc, DSMR, value);
dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
| ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)| ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)| DSMR_DIPM_DISP | DSMR_CSPM;rcar_du_crtc_write(rcrtc, DSMR, dsmr);
/* Display timings */ rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);