From: Ville Syrjälä ville.syrjala@linux.intel.com
To make the logs a bit less confusing let's toss in some debug prints to indicate whether the cdclk reprogramming is going to happen with a single pipe active or whether we need to turn all pipes off for the duration.
Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c7c46b382738..f2910c0c3e3e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2696,6 +2696,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) return ret;
state->cdclk.pipe = pipe; + + DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n", + pipe_name(pipe)); } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual, &state->cdclk.actual)) { ret = intel_modeset_all_pipes(state); @@ -2703,6 +2706,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) return ret;
state->cdclk.pipe = INVALID_PIPE; + + DRM_DEBUG_KMS("Modeset required for cdclk change\n"); }
DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",