Re: [PATCH v3] arm64: dts: qcom: sc7180: Add A618 gpu dt blob

On 2020-02-01 03:13, Doug Anderson wrote:

Hi,

On Fri, Jan 31, 2020 at 4:04 AM Sharat Masetty smasetty@codeaurora.org wrote:

...

•           adreno_smmu: iommu@5040000 {
  

•                   compatible = "qcom,sc7180-smmu-v2", 
  

"qcom,smmu-v2";

•                   reg = <0 0x05040000 0 0x10000>;
  

•                   #iommu-cells = <1>;
  

•                   #global-interrupts = <2>;
  

•                   interrupts = <GIC_SPI 229 
  

IRQ_TYPE_LEVEL_HIGH>,

•                                   <GIC_SPI 231 
  

IRQ_TYPE_LEVEL_HIGH>,

•                                   <GIC_SPI 364 
  

IRQ_TYPE_EDGE_RISING>,

•                                   <GIC_SPI 365 
  

IRQ_TYPE_EDGE_RISING>,

•                                   <GIC_SPI 366 
  

IRQ_TYPE_EDGE_RISING>,

•                                   <GIC_SPI 367 
  

IRQ_TYPE_EDGE_RISING>,

•                                   <GIC_SPI 368 
  

IRQ_TYPE_EDGE_RISING>,

•                                   <GIC_SPI 369 
  

IRQ_TYPE_EDGE_RISING>,

•                                   <GIC_SPI 370 
  

IRQ_TYPE_EDGE_RISING>,

•                                   <GIC_SPI 371 
  

IRQ_TYPE_EDGE_RISING>;

•                   clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
  

•                           <&gcc GCC_GPU_CFG_AHB_CLK>,
  

•                           <&gcc GCC_DDRSS_GPU_AXI_CLK>;
  

•                   clock-names = "bus", "iface", "mem_iface_clk";
  

Repeated comment from v2 feedback:

Please send a patch to:

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

...adding 'qcom,sc7180-smmu-v2'. If you do this it will point out that you've added a new clock: "mem_iface_clk". Is this truly a new clock in sc7180 compared to previous IOMMUs? ...or is it not really needed?

I can confirm that this clock is needed for SC7180. I will send out a new patch to update the documentation this week.

...

•           gmu: gmu@506a000 {
  

•                   compatible="qcom,adreno-gmu-618.0", 
  

"qcom,adreno-gmu";

•                   reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 
  

0 0x10000>,

•                           <0 0x0b490000 0 0x10000>;
  

•                   reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
  

•                   interrupts = <GIC_SPI 304 
  

IRQ_TYPE_LEVEL_HIGH>,

•                              <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
  

•                   interrupt-names = "hfi", "gmu";
  

•                   clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
  

•                          <&gpucc GPU_CC_CXO_CLK>,
  

•                          <&gcc GCC_DDRSS_GPU_AXI_CLK>,
  

•                          <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
  

•                   clock-names = "gmu", "cxo", "axi", "memnoc";
  

•                   power-domains = <&gpucc CX_GDSC>;
  

•                   power-domain-names = "cx";
  

As per continued comments on v2, please see if this works for you:

power-domains = <&gpucc CX_GDSC>, <0>; power-domain-names = "cx", "gx";

...and work to get something more real for "gx" ASAP. It did seem to boot for me and (unless someone disagrees) it seems better than totally leaving it out / violating the bindings?

-Doug