Re: [PATCH v4,1/3] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml

On Sat, Apr 09, 2022 at 05:11:52PM +0800, xinlei.lee@mediatek.com wrote:

From: Xinlei Lee xinlei.lee@mediatek.com

Convert mediatek,dsi.txt to mediatek,dsi.yaml format

Signed-off-by: Xinlei Lee xinlei.lee@mediatek.com

.../display/mediatek/mediatek,dsi.txt | 62 --------- .../display/mediatek/mediatek,dsi.yaml | 118 ++++++++++++++++++ 2 files changed, 118 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml new file mode 100644 index 000000000000..431bb981394f --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#

+title: MediaTek DSI Controller Device Tree Bindings

+maintainers:

• • CK Hu ck.hu@mediatek.com
• • Jitao Shi jitao.shi@mediatek.com
• • Xinlei Lee xinlei.lee@mediatek.com

+description: |

• The MediaTek DSI function block is a sink of the display subsystem and can
• drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
• channel output.

allOf: - $ref: /schemas/display/dsi-controller.yaml#

+properties:

• compatible:
• enum:

•  - mediatek,mt2701-dsi
  

•  - mediatek,mt7623-dsi
  

•  - mediatek,mt8167-dsi
  

•  - mediatek,mt8173-dsi
  

•  - mediatek,mt8183-dsi
  

• reg:
• maxItems: 1
• interrupts:
• maxItems: 1
• power-domains:
• maxItems: 1
• clocks:
• items:

•  - description: Engine Clock
  

•  - description: Digital Clock
  

•  - description: HS Clock
  

• clock-names:
• items:

•  - const: engine
  

•  - const: digital
  

•  - const: hs
  

• resets:
• maxItems: 1
• phys:
• maxItems: 1
• phy-names:
• items:

•  - const: dphy
  

• port:
• $ref: /schemas/graph.yaml#/properties/port
• description:

•  Output port node. This port should be connected to the input
  

•  port of an attached DSI panel or DSI-to-eDP encoder chip.
  

• "#address-cells":
• const: 2
• "#size-cells":
• const: 2

+required:

• • compatible
• • reg
• • interrupts
• • power-domains
• • clocks
• • clock-names
• • phys
• • phy-names
• • port

+additionalProperties: false

with the above,

unevaluatedProperties: false

+examples:

• • |
• #include <dt-bindings/clock/mt8183-clk.h>
• #include <dt-bindings/interrupt-controller/arm-gic.h>
• #include <dt-bindings/interrupt-controller/irq.h>
• #include <dt-bindings/power/mt8183-power.h>
• #include <dt-bindings/phy/phy.h>
• #include <dt-bindings/reset/mt8183-resets.h>
• soc {

•    #address-cells = <2>;
  

•    #size-cells = <2>;
  

•    dsi0: dsi@14014000 {
  

•        compatible = "mediatek,mt8183-dsi";
  

•        reg = <0 0x14014000 0 0x1000>;
  

•        interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
  

•        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
  

•        clocks = <&mmsys CLK_MM_DSI0_MM>,
  

•            <&mmsys CLK_MM_DSI0_IF>,
  

•            <&mipi_tx0>;
  

•        clock-names = "engine", "digital", "hs";
  

•        resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
  

•        phys = <&mipi_tx0>;
  

•        phy-names = "dphy";
  

•        port {
  

•            dsi0_out: endpoint {
  

•                remote-endpoint = <&panel_in>;
  

•            };
  

•        };
  

•    };
  

• };

+...

2.18.0