13 May
2020
13 May
'20
9:28 a.m.
On Wed, 13 May 2020 at 08:19, Daniel Vetter daniel@ffwll.ch wrote:
i915 is even worse, we manually mess around with clflush. In userspace. So really there's 2 axis for dma memory: coherent vs. non-coherent (which is something the dma-api somewhat exposed), i.e. do you need to clflush or not, and cached vs uncached, i.e. are the PAT entries wc or wb.
So, the PowerPC AGP GART ends up being cached and non-coherent, right (assuming there's no way to set the page attributes MTRR/PAT-style)? Would something like a fixed memory carve-out help in these cases (like CMA, but not allowing the CPU to access the reserved area)? Not that I expect something like that to ever be implemented, of course, just curious to understand the requirements.