Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote:
From: Yongqiang Niu yongqiang.niu@mediatek.com
Here is two modifition in this patch: 1.bls->dpi0 and rdma1->dsi are differen usecase, Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase 2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and this is same with hardware defautl setting,
Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index 4866a9b..c93e1b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -392,10 +392,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs, } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, config_regs + DISP_REG_CONFIG_OUT_SEL);
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { writel_relaxed(DSI_SEL_IN_RDMA, config_regs + DISP_REG_CONFIG_DSI_SEL);
writel_relaxed(DPI_SEL_IN_BLS,config_regs + DISP_REG_CONFIG_DPI_SEL);
As internal discussion, please rewrite this to prevent breaking MT2701 connection. It's better to add comment to address the special usage for MT2701.
Regards, CK
} }