From: Thierry Reding treding@nvidia.com
Tegra186 and later are different from earlier generations in that they use an ARM SMMU rather than the Tegra SMMU. The ARM SMMU driver behaves slightly differently in that the geometry for IOMMU domains is set only after a device was attached to it. This is to make sure that the SMMU instance that the domain belongs to is known, because each instance can have a different input address space (i.e. geometry).
Work around this by moving all IOVA allocations to a point where the geometry of the domain is properly initialized.
This second version of the series addresses all review comments and adds a number of patches that will actually allow host1x to work with an SMMU enabled on Tegra186. The patches also add programming required to address the full 40 bits of address space.
The third version of the series fixes the 40-bit addressing code by making sure that wide opcodes are always written atomically to the push buffer. Another pair of patches are introduced to fix a long-standing bug where the HOST1X_CHANNEL_DMAEND register wasn't properly programmed and one push buffer memory optimization that avoid wasting almost one full memory page per push buffer.
This supersedes the following patch:
https://patchwork.kernel.org/patch/10775579/
Thierry
Thierry Reding (16): gpu: host1x: Set up stream ID table gpu: host1x: Program the channel stream ID gpu: host1x: Introduce support for wide opcodes gpu: host1x: Support 40-bit addressing gpu: host1x: Use direct DMA with IOMMU API usage gpu: host1x: Restrict IOVA space to DMA mask gpu: host1x: Support 40-bit addressing on Tegra186 gpu: host1x: Use correct semantics for HOST1X_CHANNEL_DMAEND gpu: host1x: Optimize CDMA push buffer memory usage drm/tegra: Store parent pointer in Tegra DRM clients drm/tegra: vic: Load firmware on demand drm/tegra: Setup shared IOMMU domain after initialization drm/tegra: Restrict IOVA space to DMA mask drm/tegra: vic: Do not clear driver data drm/tegra: vic: Support stream ID register programming arm64: tegra: Enable SMMU for VIC on Tegra186
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + drivers/gpu/drm/tegra/drm.c | 57 +++++---- drivers/gpu/drm/tegra/drm.h | 1 + drivers/gpu/drm/tegra/vic.c | 75 ++++++++--- drivers/gpu/drm/tegra/vic.h | 9 ++ drivers/gpu/host1x/cdma.c | 132 ++++++++++++++++++-- drivers/gpu/host1x/cdma.h | 2 + drivers/gpu/host1x/dev.c | 49 +++++++- drivers/gpu/host1x/dev.h | 8 ++ drivers/gpu/host1x/hw/cdma_hw.c | 32 ++++- drivers/gpu/host1x/hw/channel_hw.c | 42 ++++++- drivers/gpu/host1x/hw/host1x06_hardware.h | 6 + drivers/gpu/host1x/hw/host1x07_hardware.h | 6 + drivers/gpu/host1x/hw/hw_host1x06_channel.h | 11 ++ drivers/gpu/host1x/hw/hw_host1x07_channel.h | 11 ++ include/trace/events/host1x.h | 26 ++++ 16 files changed, 404 insertions(+), 64 deletions(-) create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_channel.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x07_channel.h