Re: [PATCH v3 17/24] drm/sun4i: Don't change clock bits in DW HDMI PHY driver

Dne četrtek, 28. junij 2018 ob 04:24:02 CEST je Chen-Yu Tsai napisal(a):

On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec jernej.skrabec@siol.net

wrote:

...

DW HDMI PHY driver and PHY clock driver share same registers. Make sure that DW HDMI PHY setup code doesn't change any clock related bits. During initialization, set PHY PLL parent bit to 0.

Signed-off-by: Jernej Skrabec jernej.skrabec@siol.net

Reviewed-by: Chen-Yu Tsai wens@csie.org

and maybe a fixes tag?

No need for fixes tag here. H3 and H5 HDMI PHYs have only one possible parent clock. Without this patch, 0 is always written in parent clock bit, which correctly selects first parent.

This is preparation patch for 2 clock parents support.

Best regards, Jernej