The Xe_HP architecture introduces compute engines as a new engine class. These compute command streamers (CCS) are similar to the render engine, except that they're intended for GPGPU usage and lack support for the 3D pipeline.
The definition of I915_ENGINE_CLASS_COMPUTE is new ABI; see below for a link to a UMD (compute) merge request that utilizes the new ABI.
This series adds some of the basic enablement for the CCS engines, but does not yet add them to the engine list for the relevant platforms (XeHP SDV and DG2); that will be handled in future series.
UMD (compute): https://github.com/intel/compute-runtime/pull/451
Daniele Ceraolo Spurio (1): drm/i915/xehp: compute engine pipe_control
John Harrison (1): drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS
Matt Roper (6): drm/i915/xehp: Define compute class and engine drm/i915/xehp: CCS shares the render reset domain drm/i915/xehp: Add Compute CS IRQ handlers drm/i915/xehp: CCS should use RCS setup functions drm/i915/xehp: Define context scheduling attributes in lrc descriptor drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE
.../drm/i915/gem/selftests/i915_gem_context.c | 8 ++-- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 31 ++++++++++----- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 39 ++++++++++++++++++- drivers/gpu/drm/i915/gt/intel_engine_types.h | 11 +++++- drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 ++- .../drm/i915/gt/intel_execlists_submission.c | 34 +++++++++++++++- drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 15 +++++++ drivers/gpu/drm/i915/gt/intel_gt_irq.c | 15 ++++++- drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +- drivers/gpu/drm/i915/gt/intel_lrc.h | 10 +++++ drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++ drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 13 ++++--- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 28 ++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_perf.c | 4 +- drivers/gpu/drm/i915/i915_reg.h | 20 +++++++++- include/uapi/drm/i915_drm.h | 1 + 17 files changed, 215 insertions(+), 29 deletions(-)