Let's add support for being able to read the HPD pin even if it's hooked directly to the controller. This will let us take away the waiting in the AUX transfer functions of the eDP controller drivers.
Signed-off-by: Douglas Anderson dianders@chromium.org ---
.../gpu/drm/panel/panel-samsung-atna33xc20.c | 35 +++++++++++++++---- 1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c b/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c index 20666b6217e7..f72bdd7ff7a1 100644 --- a/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c +++ b/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c @@ -30,6 +30,7 @@ struct atana33xc20_panel {
struct regulator *supply; struct gpio_desc *el_on3_gpio; + struct drm_dp_aux *aux;
struct edid *edid;
@@ -76,6 +77,19 @@ static int atana33xc20_suspend(struct device *dev) return 0; }
+static bool atana33xc20_can_read_hpd(struct atana33xc20_panel *p) +{ + return !p->no_hpd && (p->hpd_gpio || p->aux->is_hpd_asserted); +} + +static bool panel_edp_read_hpd(struct atana33xc20_panel *p) +{ + if (p->hpd_gpio) + return gpiod_get_value_cansleep(p->hpd_gpio); + + return p->aux->is_hpd_asserted(p->aux); +} + static int atana33xc20_resume(struct device *dev) { struct atana33xc20_panel *p = dev_get_drvdata(dev); @@ -92,17 +106,24 @@ static int atana33xc20_resume(struct device *dev)
/* * Handle HPD. Note: if HPD is hooked up to a dedicated pin on the - * eDP controller then "no_hpd" will be false _and_ "hpd_gpio" will be - * NULL. It's up to the controller driver to wait for HPD after - * preparing the panel in that case. + * eDP controller then it's possible that "no_hpd" will be false _and_ + * atana33xc20_can_read_hpd() will return false. It's up to the + * controller driver to wait for HPD after preparing the panel in that + * case. */ if (p->no_hpd) { /* T3 VCC to HPD high is max 200 ms */ msleep(200); - } else if (p->hpd_gpio) { - ret = readx_poll_timeout(gpiod_get_value_cansleep, p->hpd_gpio, + } else if (atana33xc20_can_read_hpd(p)) { + /* + * Even though max HPD is 200 ms, we give an extra long timeout + * of 500 ms here. Why? ps8640 is crazy and the bridge chip + * driver itself has over 200 ms of delay if it needs to + * do the pm_runtime resume of the bridge chip to read the HPD. + */ + ret = readx_poll_timeout(panel_edp_read_hpd, p, hpd_asserted, hpd_asserted, - 1000, 200000); + 1000, 500000); if (!hpd_asserted) dev_warn(dev, "Timeout waiting for HPD\n"); } @@ -263,6 +284,8 @@ static int atana33xc20_probe(struct dp_aux_ep_device *aux_ep) return -ENOMEM; dev_set_drvdata(dev, panel);
+ panel->aux = aux_ep->aux; + panel->supply = devm_regulator_get(dev, "power"); if (IS_ERR(panel->supply)) return dev_err_probe(dev, PTR_ERR(panel->supply),