s/configurarion/configuration/ s/inerrupts/interrupts/ s/chanels/channels/ ....two different places. s/Synopsys/Synopsis/
Signed-off-by: Bhaskar Chowdhury unixbhaskar@gmail.com --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index d9e4ac3edb4e..ef4da10361a7 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -35,7 +35,7 @@ /* * The set of bus widths supported by the DMA controller. DW AXI DMAC supports * master data bus width up to 512 bits (for both AXI master interfaces), but - * it depends on IP block configurarion. + * it depends on IP block configuration. */ #define AXI_DMA_BUSWIDTHS \ (DMA_SLAVE_BUSWIDTH_1_BYTE | \ @@ -1056,10 +1056,10 @@ static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
u32 status, i;
- /* Disable DMAC inerrupts. We'll enable them after processing chanels */ + /* Disable DMAC interrupts. We'll enable them after processing channels */ axi_dma_irq_disable(chip);
- /* Poll, clear and process every chanel interrupt status */ + /* Poll, clear and process every channel interrupt status */ for (i = 0; i < dw->hdata->nr_channels; i++) { chan = &dw->chan[i]; status = axi_chan_irq_read(chan); @@ -1511,5 +1511,5 @@ static struct platform_driver dw_driver = { module_platform_driver(dw_driver);
MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver"); +MODULE_DESCRIPTION("Synopsis DesignWare AXI DMA Controller platform driver"); MODULE_AUTHOR("Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com"); -- 2.26.3