On 9/14/21 6:39 PM, Rob Herring wrote:
On Fri, Sep 10, 2021 at 01:42:45PM +0300, Mikko Perttunen wrote:
Add YAML device tree bindings for NVDEC, now in a more appropriate place compared to the old textual Host1x bindings.
Signed-off-by: Mikko Perttunen mperttunen@nvidia.com
v5:
- Changed from nvidia,instance to nvidia,host1x-class optional property.
- Added dma-coherent
v4:
- Fix incorrect compatibility string in 'if' condition
v3:
- Drop host1x bindings
- Change read2 to read-1 in interconnect names
v2:
- Fix issues pointed out in v1
- Add T194 nvidia,instance property
.../gpu/host1x/nvidia,tegra210-nvdec.yaml | 104 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml new file mode 100644 index 000000000000..f1f8d083d736 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+title: Device tree binding for NVIDIA Tegra NVDEC
+description: |
- NVDEC is the hardware video decoder present on NVIDIA Tegra210
- and newer chips. It is located on the Host1x bus and typically
- programmed through Host1x channels.
+maintainers:
- Thierry Reding treding@gmail.com
- Mikko Perttunen mperttunen@nvidia.com
+properties:
- $nodename:
- pattern: "^nvdec@[0-9a-f]*$"
- compatible:
- enum:
- nvidia,tegra210-nvdec- nvidia,tegra186-nvdec- nvidia,tegra194-nvdec- reg:
- maxItems: 1
- clocks:
- maxItems: 1
- clock-names:
- items:
- const: nvdec- resets:
- maxItems: 1
- reset-names:
- items:
- const: nvdec- power-domains:
- maxItems: 1
- iommus:
- maxItems: 1
- dma-coherent: true
- interconnects:
- items:
- description: DMA read memory client- description: DMA read 2 memory client- description: DMA write memory client- interconnect-names:
- items:
- const: dma-mem- const: read-1- const: write- nvidia,host1x-class:
- description: Host1x class of the engine. If not specified, defaults to 0xf0.
Define what this is with more than just repeating what is in the property name.
Sure, I'll add a description.
- $ref: /schemas/types.yaml#/definitions/uint32
default: 0xf0
Is there a range or set of valid values you specify as schema?
Only to the same extent that there is a set of valid MMIO addresses in the 'reg' field.
Mikko
Rob