Signed-off-by: mark yao yzq@rock-chips.com --- .../devicetree/bindings/video/rockchip-panel.txt | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/video/rockchip-panel.txt b/Documentation/devicetree/bindings/video/rockchip-panel.txt index 9fc200a..f599806 100644 --- a/Documentation/devicetree/bindings/video/rockchip-panel.txt +++ b/Documentation/devicetree/bindings/video/rockchip-panel.txt @@ -50,3 +50,33 @@ Example: };
}; + +Rockchip RK3288 LVDS interface +================================ +Required properties: +-compatible: "rockchip,rk3288-lvds"; + +- reg: physical base address of the controller and length +- clocks: from common clock binding: handle to dp clock. + of memory mapped region. +- clock-names: from common clock binding: Shall be "pclk_lvds". + pclk_lvds: for power domain, if it disable soc will power down +- rockchip,grf: this soc should set GRF regs, so need get grf here. +- rockchip,data-mapping: should be "vesa" or "jeida" + This describes how the color bits are laid out in the + serialized LVDS signal. +- rockchip,data-width: should be <18> or <24> +- rockchip,panel: required a panel node + +Example: + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; + reg = <0xff96c000 0x4000>; + clocks = <&cru PCLK_LVDS_PHY>; + clock-names = "pclk_lvds"; + + rockchip,grf = <&grf>; + rockchip,data-mapping = "jeida"; + rockchip,data-width = <24>; + rockchip,panel = <&panel>; + };