From: Gustavo Padovan gustavo.padovan@collabora.co.uk
ideal_clk is the divisor in an operation to find the clock divider so it can't never be zero or we will end up with a division by zero error.
Signed-off-by: Gustavo Padovan gustavo.padovan@collabora.co.uk --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 08f7197..294f9cf 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -309,6 +309,8 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx, unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh; u32 clkdiv;
+ WARN_ON(ideal_clk == 0); + if (ctx->i80_if) { /* * The frame done interrupt should be occurred prior to the