Hi, Guillaume:
On Mon, 2022-05-23 at 12:47 +0200, Guillaume Ranquet wrote:
From: Markus Schneider-Pargmann msp@baylibre.com
This patch adds a DisplayPort driver for the Mediatek mt8195 SoC.
It supports the mt8195, the embedded DisplayPort units. It offers DisplayPort 1.4 with up to 4 lanes.
The driver creates a child device for the phy. The child device will never exist without the parent being active. As they are sharing a register range, the parent passes a regmap pointer to the child so that both can work with the same register range. The phy driver sets device data that is read by the parent to get the phy device that can be used to control the phy properties.
This driver is based on an initial version by Jason-JH.Lin jason-jh.lin@mediatek.com.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com Signed-off-by: Guillaume Ranquet granquet@baylibre.com
[snip]
+static void mtk_dp_read_link_status(struct mtk_dp *mtk_dp,
u8link_status[DP_LINK_STATUS_SIZE]) +{
- drm_dp_dpcd_read(&mtk_dp->aux, DP_LANE0_1_STATUS, link_status,
DP_LINK_STATUS_SIZE);+}
+static int mtk_dp_train_tps_1(struct mtk_dp *mtk_dp,
u8 target_lane_count, int*iteration_count, u8 *lane_adjust, int *status_control, u8 *prev_lane_adjust) +{
- int ret;
- u8 val;
- u8 link_status[DP_LINK_STATUS_SIZE] = {};
- ret = mtk_dp_training_set_scramble(mtk_dp, false);
- if (ret)
return ret;- if (*status_control == 0) {
ret = mtk_dp_train_set_pattern(mtk_dp, 1);if (ret)return ret;val = DP_LINK_SCRAMBLING_DISABLE |DP_TRAINING_PATTERN_1;drm_dp_dpcd_writeb(&mtk_dp->aux,DP_TRAINING_PATTERN_SET,DP_LINK_SCRAMBLING_DISABLE |DP_TRAINING_PATTERN_1);drm_dp_dpcd_read(&mtk_dp->aux,DP_ADJUST_REQUEST_LANE0_1,lane_adjust,sizeof(*lane_adjust) * 2);mtk_dp_train_update_swing_pre(mtk_dp,target_lane_count,lane_adjust);
*status_control = 1;(*iteration_count)++;- }
- drm_dp_link_train_clock_recovery_delay(&mtk_dp->aux,
mtk_dp->rx_cap);- mtk_dp_read_link_status(mtk_dp, link_status);
drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
- if (drm_dp_clock_recovery_ok(link_status,
target_lane_count)) {mtk_dp->train_info.cr_done = true;*iteration_count = 1;dev_dbg(mtk_dp->dev, "Link train CR pass\n");return 0;- } else if (*prev_lane_adjust == link_status[4]) {
(*iteration_count)++;if (*prev_lane_adjust &DP_ADJUST_VOLTAGE_SWING_LANE0_MASK) {
dev_dbg(mtk_dp->dev, "Link train CQ fail\n");return -EINVAL;}- } else {
*prev_lane_adjust = link_status[4];- }
- return -EAGAIN;
+}
+static int mtk_dp_train_tps_2_3(struct mtk_dp *mtk_dp, u8 target_linkrate,
u8 target_lane_count, int*iteration_count, u8 *lane_adjust, int *status_control, u8 *prev_lane_adjust) +{
- int ret;
- u8 val;
- u8 link_status[DP_LINK_STATUS_SIZE] = {};
- if (*status_control == 1) {
if (mtk_dp->train_info.tps4) {ret = mtk_dp_train_set_pattern(mtk_dp, 4);if (ret)return -EINVAL;val = DP_TRAINING_PATTERN_4;} else if (mtk_dp->train_info.tps3) {ret = mtk_dp_train_set_pattern(mtk_dp, 3);if (ret)return -EINVAL;val = DP_LINK_SCRAMBLING_DISABLE |DP_TRAINING_PATTERN_3;} else {ret = mtk_dp_train_set_pattern(mtk_dp, 2);if (ret)return -EINVAL;val = DP_LINK_SCRAMBLING_DISABLE |DP_TRAINING_PATTERN_2;}drm_dp_dpcd_writeb(&mtk_dp->aux,DP_TRAINING_PATTERN_SET,val);drm_dp_dpcd_read(&mtk_dp->aux,DP_ADJUST_REQUEST_LANE0_1,lane_adjust,sizeof(*lane_adjust) * 2);mtk_dp_train_update_swing_pre(mtk_dp,target_lane_count,lane_adjust);
*status_control = 2;(*iteration_count)++;- }
- drm_dp_link_train_channel_eq_delay(&mtk_dp->aux,
mtk_dp->rx_cap);- mtk_dp_read_link_status(mtk_dp, link_status);
drm_dp_dpcd_read_link_status(&mtk_dp->aux, link_status);
Regards, CK
- if (!drm_dp_clock_recovery_ok(link_status,
target_lane_count)) {mtk_dp->train_info.cr_done = false;mtk_dp->train_info.eq_done = false;dev_dbg(mtk_dp->dev, "Link train EQ fail\n");return -EINVAL;- }
- if (drm_dp_channel_eq_ok(link_status,
target_lane_count)) {mtk_dp->train_info.eq_done = true;dev_dbg(mtk_dp->dev, "Link train EQ pass\n");return 0;- }
- if (*prev_lane_adjust == link_status[4])
(*iteration_count)++;- else
*prev_lane_adjust = link_status[4];- return -EAGAIN;
+}