From: Ville Syrjälä ville.syrjala@linux.intel.com
Once we do the hw vs. uapi split we can no longer use drm_atomic_helper_calc_timestamping_constants() as it'll consult the uapi state instead of the hw state.
So let's just update the vblank timestamping constants whenever we update the scanline offset. We use both to convert the hw scanline count to something which matches the software timing values.
First I thought to put these into intel_crtc_vblank_on() but we may want to get the scanline counter value before that (eg. from some early tracepoints), so let's stick to updating them a bit earlier than intel_crtc_vblank_on().
Signed-off-by: Ville Syrjälä ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b80d864cc8f1..ae5fa584d9ae 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -13361,10 +13361,15 @@ intel_modeset_verify_disabled(struct drm_i915_private *dev_priv, verify_disabled_dpll_state(dev_priv); }
-static void update_scanline_offset(const struct intel_crtc_state *crtc_state) +static void +intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + + drm_calc_timestamping_constants(&crtc->base, adjusted_mode);
/* * The scanline counter increments at the leading edge of hsync. @@ -13394,7 +13399,6 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state) * answer that's slightly in the future. */ if (IS_GEN(dev_priv, 2)) { - const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; int vtotal;
vtotal = adjusted_mode->crtc_vtotal; @@ -13405,8 +13409,9 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state) } else if (HAS_DDI(dev_priv) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { crtc->scanline_offset = 2; - } else + } else { crtc->scanline_offset = 1; + } }
static void intel_modeset_clear_plls(struct intel_atomic_state *state) @@ -13707,7 +13712,8 @@ static void intel_update_crtc(struct intel_crtc *crtc, to_intel_plane(crtc->base.primary));
if (modeset) { - update_scanline_offset(new_crtc_state); + intel_crtc_update_active_timings(new_crtc_state); + dev_priv->display.crtc_enable(new_crtc_state, state);
/* vblanks work again, re-enable pipe CRC. */ @@ -13980,7 +13986,6 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset) { drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); - drm_atomic_helper_calc_timestamping_constants(&state->base);
intel_set_cdclk_pre_plane_update(dev_priv, &state->cdclk.actual, @@ -16787,9 +16792,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) min_cdclk = 0; }
- drm_calc_timestamping_constants(&crtc->base, - &crtc_state->base.adjusted_mode); - update_scanline_offset(crtc_state); + intel_crtc_update_active_timings(crtc_state); }
dev_priv->min_cdclk[crtc->pipe] = min_cdclk;