To get HDMI YCBCR420 output, the PIPEMISC register should be programmed to: - Generate YCBCR output (bit 11) - In case of YCBCR420 outputs, it should be programmed in full blend mode to use the scaler in 5x3 ratio (bits 26 and 27)
This patch: - Adds definition of these bits. - Programs PIPEMISC for YCBCR outputs.
V2: rebase V3: rebase V4: rebase
Cc: Ville Syrjala ville.syrjala@linux.intel.com Cc: Ander Conselvan De Oliveira ander.conselvan.de.oliveira@intel.com Cc: Daniel Vetter daniel.vetter@intel.com Signed-off-by: Shashank Sharma shashank.sharma@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_display.c | 9 +++++++++ 2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 88e4707..77921ec 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5196,6 +5196,9 @@ enum {
#define _PIPE_MISC_A 0x70030 #define _PIPE_MISC_B 0x71030 +#define PIPEMISC_YCBCR420_ENABLE (1<<27) +#define PIPEMISC_YCBCR420_MODE_BLEND (1<<26) +#define PIPEMISC_OUTPUT_YCBCR (1<<11) #define PIPEMISC_DITHER_BPC_MASK (7<<5) #define PIPEMISC_DITHER_8_BPC (0<<5) #define PIPEMISC_DITHER_10_BPC (1<<5) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 983f581..71fd19e 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8109,6 +8109,15 @@ static void haswell_set_pipemisc(struct drm_crtc *crtc) if (intel_crtc->config->dither) val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
+ if (hdmi_out > DRM_HDMI_OUTPUT_DEFAULT_RGB) { + val |= PIPEMISC_OUTPUT_YCBCR; + + if (hdmi_out == DRM_HDMI_OUTPUT_YCBCR420) { + val |= PIPEMISC_YCBCR420_ENABLE | + PIPEMISC_YCBCR420_MODE_BLEND; + } + } + I915_WRITE(PIPEMISC(intel_crtc->pipe), val); } }