--- drivers/gpu/drm/radeon/evergreen_reg.h | 3 +++ drivers/gpu/drm/radeon/r600_hdmi.c | 16 ++++++++++------ 2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h index b883911..2dc1365 100644 --- a/drivers/gpu/drm/radeon/evergreen_reg.h +++ b/drivers/gpu/drm/radeon/evergreen_reg.h @@ -198,4 +198,7 @@ #define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 #define EVERGREEN_DC_GPIO_HPD_Y 0x64bc
+#define EVERGREEN_HDMI_BLOCK1 0x7c30 +#define EVERGREEN_HDMI_CONFIG1 0x7d20 + #endif diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 5021372..fe9c7bc 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c @@ -313,7 +313,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod struct radeon_device *rdev = dev->dev_private; uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
- if (ASIC_IS_DCE4(rdev)) + if (ASIC_IS_DCE5(rdev)) return;
if (!offset) @@ -463,7 +463,9 @@ static void r600_hdmi_assign_block(struct drm_encoder *encoder) if (ASIC_IS_DCE5(rdev)) { /* TODO */ } else if (ASIC_IS_DCE4(rdev)) { - /* TODO */ + /* FIXME: what about other blocks? */ + radeon_encoder->hdmi_offset = EVERGREEN_HDMI_BLOCK1; + radeon_encoder->hdmi_config_offset = EVERGREEN_HDMI_CONFIG1; } else if (ASIC_IS_DCE3(rdev)) { radeon_encoder->hdmi_offset = dig->dig_encoder ? R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1; @@ -486,7 +488,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder) struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); uint32_t offset;
- if (ASIC_IS_DCE4(rdev)) + if (ASIC_IS_DCE5(rdev)) return;
if (!radeon_encoder->hdmi_offset) { @@ -502,7 +504,9 @@ void r600_hdmi_enable(struct drm_encoder *encoder) if (ASIC_IS_DCE5(rdev)) { /* TODO */ } else if (ASIC_IS_DCE4(rdev)) { - /* TODO */ + /* FIXME: This -=0x30 is hacky, are the blocks correct? */ + WREG32_P(offset - 0x30, 0x1000, ~0x1000); + WREG32_P(radeon_encoder->hdmi_config_offset + 0xc, 0x1, ~0x1); } else if (ASIC_IS_DCE32(rdev)) { WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); } else if (ASIC_IS_DCE3(rdev)) { @@ -526,8 +530,8 @@ void r600_hdmi_enable(struct drm_encoder *encoder) if (rdev->irq.installed && rdev->family != CHIP_RS600 && rdev->family != CHIP_RS690 - && rdev->family != CHIP_RS740) { - + && rdev->family != CHIP_RS740 + && !ASIC_IS_DCE4(rdev)) { /* if irq is available use it */ rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true; radeon_irq_set(rdev);