Some eDP 1.4 panels cannot use the optimized fast and narrow pipe config approach, but they need to use th maximum supported lane count for the link training to succeed. There is a DRM EDID quirk for such panels that gets set after reading their corresponding EDID. So if it is set, this patch forces the max lane count in compute_config() hook to use max lane count for link training.
Cc: Clint Taylor Clinton.A.Taylor@intel.com Cc: Ville Syrjälä ville.syrjala@linux.intel.com Tested-by: Albert Astals Cid aacid@kde.org Tested-by: Emanuele Panigati ilpanich@gmail.com Tested-by: Ralgor ralgorfdb@compuspex.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959 Signed-off-by: Manasi Navare manasi.d.navare@intel.com --- drivers/gpu/drm/i915/intel_dp.c | 5 ++++- drivers/gpu/drm/i915/intel_drv.h | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 72c49070ed14..421db00f5792 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2028,7 +2028,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, limits.min_bpp = 6 * 3; limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
- if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) { + if (intel_dp->edp_force_max_lane_count || (intel_dp_is_edp(intel_dp) && + intel_dp->edp_dpcd[0] < DP_EDP_14)) { /* * Use the maximum clock and number of lanes the eDP panel * advertizes being capable of. The eDP 1.3 and earlier panels @@ -7101,6 +7102,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, edid = drm_get_edid(connector, &intel_dp->aux.ddc); if (edid) { if (drm_add_edid_modes(connector, edid)) { + if (connector->display_info.force_max_lane_count) + intel_dp->edp_force_max_lane_count = true; drm_connector_update_edid_property(connector, edid); } else { diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index f8c7b291fdc3..c67c3c518714 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1327,6 +1327,9 @@ struct intel_dp {
/* Display stream compression testing */ bool force_dsc_en; + + /* eDP 1.4 EDID quirk to use max lane count */ + bool edp_force_max_lane_count; };
enum lspcon_vendor {