Hi Rob,
Subject: Re: [PATCH 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
On Wed, Mar 23, 2022 at 06:26:31PM +0000, Biju Das wrote:
Hi Rob,
Thanks for the feedback.
Subject: Re: [PATCH 1/2] dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
On Mon, Mar 14, 2022 at 04:10:02PM +0000, Biju Das wrote:
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family
SoC's.
It can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das biju.das.jz@bp.renesas.com
RFC->v1:
- Added a ref to dsi-controller.yaml.
RFC:-
.../bindings/display/bridge/renesas,dsi.yaml | 146 ++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam l b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yam l new file mode 100644 index 000000000000..74bc3782d230 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi +++ .yam +++ l @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML +1.2 +--- +$id:
+title: Renesas RZ/G2L MIPI DSI Encoder
+maintainers:
- Biju Das biju.das.jz@bp.renesas.com
+description: |
- This binding describes the MIPI DSI encoder embedded in the
+Renesas
- RZ/G2L family of SoC's. The encoder can operate in DSI mode
+with up
- to four data lanes.
+allOf:
- $ref: ../dsi-controller.yaml#
Full path preferred:
/schemas/display/dsi-controller.yaml#
OK. Will fix this.
+properties:
- compatible:
- enum:
- renesas,rzg2l-mipi-dsi # RZ/G2L and RZ/V2L- reg:
- items:
- description: Link register- description: D-PHY registerD-PHY is not a separate block?
Basically D-PHY is integrated inside MIPI-DSI Tx module.
MIPI-DSI Tx module consists of MIPI DSI-2 Host controller (LINK) and MIPI D-PHY Tx(D-PHY).
That is the reason I have modelled like this.
Is this model ok or am I missing something here? Please let me know.
I don't know the details of the h/w so I can't say. We do see blocks with a phy modeled as 1 block only to need to separate them when the phy part changes in the next process node. I imagine we have it done both ways for DSI + D-PHY.
Yes, Please see [1] and [2], where (DSI + D-PHY) modelled as single block.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Doc...
[2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/dri...
Regards, Biju