Get the ref clock of the PHY from the device tree instead of hardcoding its name and rate.
Signed-off-by: Matthias Kaehlcke mka@chromium.org --- Changes in v2: - patch added to the series --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c index 49008451085b8..461975c410fc4 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c @@ -47,7 +47,6 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 27000000 #define VCO_MIN_RATE 600000000 #define VCO_MAX_RATE 1200000000
@@ -75,6 +74,8 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio;
+ struct clk *vco_ref_clk; + /* custom byte clock divider */ struct clk_bytediv *bytediv;
@@ -125,7 +126,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, DBG("rate=%lu, parent's=%lu", rate, parent_rate);
temp = rate / 10; - val = VCO_REF_CLK_RATE / 10; + val = parent_rate / 10; fb_divider = (temp * VCO_PREF_DIV_RATIO) / val; fb_divider = fb_divider / 2 - 1; pll_write(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_1, @@ -409,8 +410,9 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) { char *clk_name, *parent_name, *vco_name; + const char *ref_clk_name = __clk_get_name(pll_28nm->vco_ref_clk); struct clk_init_data vco_init = { - .parent_names = (const char *[]){ "pxo" }, + .parent_names = &ref_clk_name, .num_parents = 1, .flags = CLK_IGNORE_UNUSED, .ops = &clk_ops_dsi_pll_28nm_vco, @@ -506,6 +508,15 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_8960_init(struct platform_device *pdev, pll_28nm->pdev = pdev; pll_28nm->id = id + 1;
+ pll_28nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref"); + if (IS_ERR(pll_28nm->vco_ref_clk)) { + ret = PTR_ERR(pll_28nm->vco_ref_clk); + if (ret != EPROBE_DEFER) + dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n", + ret); + return ERR_PTR(ret); + } + pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL"); if (IS_ERR_OR_NULL(pll_28nm->mmio)) { dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);