On 16-02-22, 19:44, Abhinav Kumar wrote:
On 2/10/2022 2:34 AM, Vinod Koul wrote:
When DSC is enabled, we need to configure DSI registers accordingly and configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and timing information and configure these registers.
Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul vkoul@kernel.org
drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++ drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++- 2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 49b551ad1bff..c1c85df58c4b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) #define REG_DSI_CPHY_MODE_CTRL 0x000002d4 +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
+#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
This file should not be edited manually. The updates have to be generated using the headergen tool.
I have already send mesa patch for that. https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14967#note_1253974 You should chime in there as well :)
I will split these and get these generated one as a separate patch..
#endif /* DSI_XML */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 438c80750682..3d8d5a1daaa3 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); } +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
int pic_width, int pic_height)+{
- if (!dsc || !pic_width || !pic_height) {
pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);return -EINVAL;- }
- dsc->drm->pic_width = pic_width;
- dsc->drm->pic_height = pic_height;
- return 0;
+}
- static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) { struct drm_display_mode *mode = msm_host->mode;
@@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) hdisplay /= 2; }
- if (msm_host->dsc) {
struct msm_display_dsc_config *dsc = msm_host->dsc;/* update dsc params with timing params */dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);/* we do the calculations for dsc parameters here so that* panel can use these parameters*/dsi_populate_dsc_params(dsc);/* Divide the display by 3 but keep back/font porch and* pulse width same*/h_total -= hdisplay;hdisplay /= 3;h_total += hdisplay;ha_end = ha_start + hdisplay;- }
- if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
if (msm_host->dsc) {struct msm_display_dsc_config *dsc = msm_host->dsc;u32 reg, intf_width, slice_per_intf;u32 total_bytes_per_intf;/* first calculate dsc parameters and then program* compress mode registers*/intf_width = hdisplay;slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);dsc->drm->slice_count = 1;Why is this hard-coded to 1 here? Am i missing something? I think I need another day to look into these calculations.
Thanks for spotting this, it should be: dsc->drm->slice_count = DIV_ROUND_UP(intf_width, dsc->drm->slice_widths);
which is slice_per_intf so I will update this