Hello Alex Deucher,
The patch aaa36a976bbb: "drm/amdgpu: Add initial VI support" from Apr 20, 2015, leads to the following static checker warning:
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c:260 gmc_v8_0_mc_load_microcode() warn: we tested 'running' before and it was 'false'
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 257 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 258 259 if (running == 0) { ^^^^^^^^^^^^ 260 if (running) { ^^^^^^^ Never true.
261 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 262 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 263 } 264 265 /* reset the engine and set to writable */ 266 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 267 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 268 269 /* load mc io regs */ 270 for (i = 0; i < regs_size; i++) { 271 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 272 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 273 } 274 /* load the MC ucode */ 275 for (i = 0; i < ucode_size; i++) 276 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 277 278 /* put the engine back into the active state */ 279 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 280 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 281 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 282 283 /* wait for training to complete */ 284 for (i = 0; i < adev->usec_timeout; i++) { 285 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 286 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 287 break; 288 udelay(1); 289 } 290 for (i = 0; i < adev->usec_timeout; i++) { 291 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 292 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 293 break; 294 udelay(1); 295 } 296 297 if (running) ^^^^^^^ Same.
298 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 299 } 300
regards, dan carpenter