19 Apr
2016
19 Apr
'16
9:18 a.m.
On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote:
On 03/23, Maxime Ripard wrote:
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.)
Add a driver for it.
Acked-by: Rob Herring robh@kernel.org Acked-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Maxime Ripard maxime.ripard@free-electrons.com
Acked-by: Stephen Boyd sboyd@codeaurora.org
Applied, thanks! Maxime
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Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com