Signed-off-by: Rafał Miłecki zajec5@gmail.com --- avivotool.c | 30 ++++++++++++++++++++++++------ radeon_reg.h | 8 +++++--- 2 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/avivotool.c b/avivotool.c index 4c5c1ce..f5b3f72 100644 --- a/avivotool.c +++ b/avivotool.c @@ -1697,13 +1697,31 @@ void radeon_cmd_regs(const char *type) SHOW_REG(R600_AUDIO_PIN_WIDGET_CNTL); SHOW_REG(R600_AUDIO_STATUS_BITS);
- printf("\nHDMI block at 0x%x:\n", R600_HDMI_BLOCK1); - for (i = R600_HDMI_BLOCK1; i < R600_HDMI_BLOCK1 + 0xf0; i += 4) - SHOW_UNKNOWN_REG(i); + if (IS_DISPLAY_DCE3(card_info)) { + printf("\nHDMI block at 0x%x:\n", DCE3_HDMI_BLOCK0); + for (i = DCE3_HDMI_BLOCK0; i <= DCE3_HDMI_BLOCK0 + 0xf0; i += 4) + SHOW_UNKNOWN_REG(i); + if (card_info && card_info->chip_family >= CHIP_FAMILY_RV730) { + for (i = DCE3_HDMI_BLOCK0 + 0x200; i <= DCE3_HDMI_BLOCK0 + 0x210; i += 4) + SHOW_UNKNOWN_REG(i); + }
- printf("\nHDMI block at 0x%x:\n", R600_HDMI_BLOCK3); - for (i = R600_HDMI_BLOCK3; i < R600_HDMI_BLOCK3 + 0xf0; i += 4) - SHOW_UNKNOWN_REG(i); + printf("\nHDMI block at 0x%x:\n", DCE3_HDMI_BLOCK1); + for (i = DCE3_HDMI_BLOCK1; i <= DCE3_HDMI_BLOCK1 + 0xf0; i += 4) + SHOW_UNKNOWN_REG(i); + if (card_info && card_info->chip_family >= CHIP_FAMILY_RV730) { + for (i = DCE3_HDMI_BLOCK1 + 0x200; i <= DCE3_HDMI_BLOCK1 + 0x210; i += 4) + SHOW_UNKNOWN_REG(i); + } + } else { + printf("\nHDMI block at 0x%x:\n", DCE2_HDMI_BLOCK0); + for (i = DCE2_HDMI_BLOCK0; i <= DCE2_HDMI_BLOCK0 + 0xf0; i += 4) + SHOW_UNKNOWN_REG(i); + + printf("\nHDMI block at 0x%x:\n", DCE2_HDMI_BLOCK1); + for (i = DCE2_HDMI_BLOCK1; i <= DCE2_HDMI_BLOCK1 + 0xf0; i += 4) + SHOW_UNKNOWN_REG(i); + } } }
diff --git a/radeon_reg.h b/radeon_reg.h index ea5b6bc..06136e3 100644 --- a/radeon_reg.h +++ b/radeon_reg.h @@ -3063,9 +3063,11 @@ #define R600_AUDIO_STATUS_BITS 0x73d8
/* HDMI base register addresses */ -#define R600_HDMI_BLOCK1 0x7400 -#define R600_HDMI_BLOCK2 0x7700 -#define R600_HDMI_BLOCK3 0x7800 +#define DCE2_HDMI_BLOCK0 0x7400 +#define DCE2_HDMI_BLOCK1 0x7700 +/* DCE3 second instance starts at 0x7800 */ +#define DCE3_HDMI_BLOCK0 0x7400 +#define DCE3_HDMI_BLOCK1 0x7800
#define RADEON_MC_ARB_CNTL 0x18c #define RADEON_PWRMAN_MISC 0x16