Am 01.08.2014 um 10:22 schrieb Michel Dänzer:
From: Michel Dänzer michel.daenzer@amd.com
The HDP cache only applies to CPU access to VRAM.
Signed-off-by: Michel Dänzer michel.daenzer@amd.com
Wanted to suggest the same thing already, looks like a valid optimization to me.
Patch is Reviewed-by: Christian König christian.koenig@amd.com
drivers/gpu/drm/radeon/radeon_gem.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index a350cf9..8f2cb58 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -359,15 +359,17 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_gem_object *gobj; struct radeon_bo *robj; int r;
uint32_t cur_placement = 0;
gobj = drm_gem_object_lookup(dev, filp, args->handle); if (gobj == NULL) { return -ENOENT; } robj = gem_to_radeon_bo(gobj);
- r = radeon_bo_wait(robj, NULL, false);
- r = radeon_bo_wait(robj, &cur_placement, false); /* Flush HDP cache via MMIO if necessary */
- if (rdev->asic->mmio_hdp_flush)
- if (rdev->asic->mmio_hdp_flush &&
radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM)