Re: [PATCH] drm/i915: Set i9xx sdvo clock limits according to specifications

On Thu, Feb 14, 2013 at 08:50:25PM +0000, Chris Wilson wrote:

On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote:

...

The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9. Since we do all calculations based on them being register values (which are subtracted by 2) we need to specify them accordingly.

Signed-off-by: Patrik Jakobsson patrik.r.jakobsson@gmail.com

Reviewed-by: Chris Wilson chris@chris-wilson.co.uk

Queued both for -next with a cc: stable tag to increase the odds of detecting bugs (or fixing some). Thanks for the patches. -Daniel

-Chris

-- Chris Wilson, Intel Open Source Technology Centre