Re: [PATCH v8 08/13] arm64: dts: mt8173: Add display subsystem related nodes

On Tue, Jan 5, 2016 at 1:36 AM, Philipp Zabel p.zabel@pengutronix.de wrote:

From: CK Hu ck.hu@mediatek.com

This patch adds the device nodes for the DISP function blocks comprising the display subsystem.

Signed-off-by: CK Hu ck.hu@mediatek.com Signed-off-by: Cawa Cheng cawa.cheng@mediatek.com Signed-off-by: Jie Qiu jie.qiu@mediatek.com Signed-off-by: Daniel Kurtz djkurtz@chromium.org Signed-off-by: Philipp Zabel p.zabel@pengutronix.de

---

Changes since v7:

• Add 26 MHz PLL reference input clock and the high-speed output clock to the MIPI TX D-PHY nodes
• The HS output clock is routed to the DSI encoder module
• Add power-domains property to all nodes in the MM domain

---

arch/arm64/boot/dts/mediatek/mt8173.dtsi | 237 +++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 4901f13..68c1cb2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -25,6 +25,23 @@ #address-cells = <2>; #size-cells = <2>;

•   aliases {
  

•           ovl0 = &ovl0;
  

•           ovl1 = &ovl1;
  

•           rdma0 = &rdma0;
  

•           rdma1 = &rdma1;
  

•           rdma2 = &rdma2;
  

•           wdma0 = &wdma0;
  

•           wdma1 = &wdma1;
  

•           color0 = &color0;
  

•           color1 = &color1;
  

•           split0 = &split0;
  

•           split1 = &split1;
  

•           dpi0 = &dpi0;
  

•           dsi0 = &dsi0;
  

•           dsi1 = &dsi1;
  

•   };
  

•   cpus {
            #address-cells = <1>;
            #size-cells = <0>;
  

@@ -285,6 +302,24 @@ #clock-cells = <1>; };

•           mipi_tx0: mipi-dphy@10215000 {
  

•                   compatible = "mediatek,mt8173-mipi-tx";
  

•                   reg = <0 0x10215000 0 0x1000>;
  

•                   clocks = <&clk26m>;
  

•                   clock-output-names = "mipi_tx0_pll";
  

•                   #clock-cells = <0>;
  

•                   #phy-cells = <0>;
  

•           };
  

•           mipi_tx1: mipi-dphy@10216000 {
  

•                   compatible = "mediatek,mt8173-mipi-tx";
  

•                   reg = <0 0x10216000 0 0x1000>;
  

•                   clocks = <&clk26m>;
  

•                   clock-output-names = "mipi_tx1_pll";
  

•                   #clock-cells = <0>;
  

•                   #phy-cells = <0>;
  

•           };
  

•           gic: interrupt-controller@10220000 {
                    compatible = "arm,gic-400";
                    #interrupt-cells = <3>;
  

@@ -431,6 +466,14 @@ status = "disabled"; };

•           hdmiddc0: i2c@11012000 {
  

•                   compatible = "mediatek,mt8173-hdmi-ddc";
  

•                   interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
  

•                   reg = <0 0x11012000 0 0x1C>;
  

•                   clocks = <&pericfg CLK_PERI_I2C5>;
  

•                   clock-names = "ddc-i2c";
  

•           };
  

•           i2c6: i2c@11013000 {
                    compatible = "mediatek,mt8173-i2c";
                    reg = <0 0x11013000 0 0x70>,
  

@@ -525,7 +568,187 @@ mmsys: clock-controller@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>;

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
                    #clock-cells = <1>;
  

•                   /* FIXME - remove iommus here */
  

•                   iommus = <&iommu M4U_PORT_DISP_OVL0>,
  

•                            <&iommu M4U_PORT_DISP_OVL1>;
  

•           };
  

•           ovl0: ovl@1400c000 {
  

•                   compatible = "mediatek,mt8173-disp-ovl";
  

•                   reg = <0 0x1400c000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_OVL0>;
  

•                   iommus = <&iommu M4U_PORT_DISP_OVL0>;
  

•                   mediatek,larb = <&larb0>;
  

•           };
  

•           ovl1: ovl@1400d000 {
  

•                   compatible = "mediatek,mt8173-disp-ovl";
  

•                   reg = <0 0x1400d000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_OVL1>;
  

•                   iommus = <&iommu M4U_PORT_DISP_OVL1>;
  

•                   mediatek,larb = <&larb4>;
  

•           };
  

•           rdma0: rdma@1400e000 {
  

•                   compatible = "mediatek,mt8173-disp-rdma";
  

•                   reg = <0 0x1400e000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_RDMA0>;
  

•                   iommus = <&iommu M4U_PORT_DISP_RDMA0>;
  

•                   mediatek,larb = <&larb0>;
  

•           };
  

•           rdma1: rdma@1400f000 {
  

•                   compatible = "mediatek,mt8173-disp-rdma";
  

•                   reg = <0 0x1400f000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_RDMA1>;
  

•                   iommus = <&iommu M4U_PORT_DISP_RDMA1>;
  

•                   mediatek,larb = <&larb4>;
  

•           };
  

•           rdma2: rdma@14010000 {
  

•                   compatible = "mediatek,mt8173-disp-rdma";
  

•                   reg = <0 0x14010000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_RDMA2>;
  

•                   iommus = <&iommu M4U_PORT_DISP_RDMA2>;
  

•                   mediatek,larb = <&larb4>;
  

•           };
  

•           wdma0: wdma@14011000 {
  

•                   compatible = "mediatek,mt8173-disp-wdma";
  

•                   reg = <0 0x14011000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_WDMA0>;
  

•                   iommus = <&iommu M4U_PORT_DISP_WDMA0>;
  

•                   mediatek,larb = <&larb0>;
  

•           };
  

•           wdma1: wdma@14012000 {
  

•                   compatible = "mediatek,mt8173-disp-wdma";
  

•                   reg = <0 0x14012000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_WDMA1>;
  

•                   iommus = <&iommu M4U_PORT_DISP_WDMA1>;
  

•                   mediatek,larb = <&larb4>;
  

•           };
  

•           color0: color@14013000 {
  

•                   compatible = "mediatek,mt8173-disp-color";
  

•                   reg = <0 0x14013000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_COLOR0>;
  

•           };
  

•           color1: color@14014000 {
  

•                   compatible = "mediatek,mt8173-disp-color";
  

•                   reg = <0 0x14014000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_COLOR1>;
  

•           };
  

•           aal@14015000 {
  

•                   compatible = "mediatek,mt8173-disp-aal";
  

•                   reg = <0 0x14015000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_AAL>;
  

•           };
  

•           gamma@14016000 {
  

•                   compatible = "mediatek,mt8173-disp-gamma";
  

•                   reg = <0 0x14016000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_GAMMA>;
  

•           };
  

•           merge@14017000 {
  

•                   compatible = "mediatek,mt8173-disp-merge";
  

•                   reg = <0 0x14017000 0 0x1000>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_MERGE>;
  

•           };
  

•           split0: split@14018000 {
  

•                   compatible = "mediatek,mt8173-disp-split";
  

•                   reg = <0 0x14018000 0 0x1000>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
  

•           };
  

•           split1: split@14019000 {
  

•                   compatible = "mediatek,mt8173-disp-split";
  

•                   reg = <0 0x14019000 0 0x1000>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
  

•           };
  

•           ufoe@1401a000 {
  

•                   compatible = "mediatek,mt8173-disp-ufoe";
  

•                   reg = <0 0x1401a000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DISP_UFOE>;
  

•           };
  

•           dsi0: dsi@1401b000 {
  

•                   compatible = "mediatek,mt8173-dsi";
  

•                   reg = <0 0x1401b000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
  

•                            <&mmsys CLK_MM_DSI0_DIGITAL>,
  

•                            <&mipi_tx0>;
  

•                   clock-names = "engine", "digital", "hs";
  

•                   phys = <&mipi_tx0>;
  

•                   phy-names = "dphy";
  

•           };
  

•           dsi1: dsi@1401c000 {
  

•                   compatible = "mediatek,mt8173-dsi";
  

•                   reg = <0 0x1401c000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
  

•                            <&mmsys CLK_MM_DSI1_DIGITAL>,
  

•                            <&mipi_tx1>;
  

•                   clock-names = "engine", "digital", "hs";
  

•                   phy = <&mipi_tx1>;
  

•                   phy-names = "dphy";
  

•                   status = "disabled";
  

•           };
  

•           dpi0: dpi@1401d000 {
  

•                   compatible = "mediatek,mt8173-dpi";
  

•                   reg = <0 0x1401d000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_DPI_PIXEL>,
  

•                            <&mmsys CLK_MM_DPI_ENGINE>,
  

•                            <&apmixedsys CLK_APMIXED_TVDPLL>;
  

•                   clock-names = "pixel", "engine", "pll";
  

•                   port {
  

•                           dpi0_out: endpoint {
  

•                                   remote-endpoint = <&hdmi0_in>;
  

nit: At this point in the patch series, you haven't defined hdmi0_in yet. Move this port to "Add HDMI related nodes".

•                           };
  

•                   };
            };
  
            pwm0: pwm@1401e000 {
  

@@ -550,6 +773,20 @@ status = "disabled"; };

•           mutex: mutex@14020000 {
  

•                   compatible = "mediatek,mt8173-disp-mutex";
  

•                   reg = <0 0x14020000 0 0x1000>;
  

•                   interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
  

•                   power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  

•                   clocks = <&mmsys CLK_MM_MUTEX_32K>;
  

•           };
  

•           od@14023000 {
  

•                   compatible = "mediatek,mt8173-disp-od";
  

•                   reg = <0 0x14023000 0 0x1000>;
  

•                   clocks = <&mmsys CLK_MM_DISP_OD>;
  

•           };
  

•           larb0: larb@14021000 {
                    compatible = "mediatek,mt8173-smi-larb";
                    reg = <0 0x14021000 0 0x1000>;
  

-- 2.6.2