On 15/06/16 11:39, Jyri Sarha wrote:
Reorder the IRQ function so that the write to LCDC_END_OF_INT_IND_REG is done last. The write to LCDC_END_OF_INT_IND_REG indicates to LCDC that the interrupt service routine has completed (see section 13.3.6.1.6 in AM335x TRM). This is needed if LCDC's ipgvmodirq module is configured for pulse interrupts.
Signed-off-by: Jyri Sarha jsarha@ti.com
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 4d8f9a5..1343717 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -725,14 +725,19 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) tilcdc_crtc->frame_intact = true; }
- if (priv->rev == 2) {
if (stat & LCDC_FRAME_DONE) {tilcdc_crtc->frame_done = true;wake_up(&tilcdc_crtc->frame_done_wq);}tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
if (priv->rev == 1)
return IRQ_HANDLED;/* The rest is for revision 2 only */
if (stat & LCDC_FRAME_DONE) {
tilcdc_crtc->frame_done = true;wake_up(&tilcdc_crtc->frame_done_wq);}
if (stat & LCDC_FIFO_UNDERFLOW)
dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",__func__, stat);
We do have underflow irq for rev1 too, don't we?
Why not just move the "if (priv->rev == 2) {" block to the end? Or maybe extract the write to the LCDC_END_OF_INT_IND_REG from the current block, and move only that to the end. Much less re-ordering needed for that.
Tomi