On Tue, Nov 27, 2018 at 10:00:50PM -0800, Doug Anderson wrote:
Hi,
On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke mka@chromium.org wrote:
@@ -409,8 +410,9 @@ static void dsi_pll_28nm_destroy(struct msm_dsi_pll *pll) static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm) { char *clk_name, *parent_name, *vco_name;
const char *ref_clk_name = __clk_get_name(pll_28nm->vco_ref_clk);IMO for the 28nm PHY driver you should probably make things work OK even if the "ref" clock wasn't supplied. In the spirit of the stable device tree it would be nice (even if nobody actually ships device trees separate from kernels). ...and also it makes the whole thing easier to land. If you add compatibility here then the code and device tree patch can go in separately.
Ok, I'll make it fall back to the 'default' values if the ref clock is not specified.