radeon framebuffer tiling

Hi,

dce4_crtc_do_set_base is the only location in which EVERGREEN_GRPH_CONTROL is updated. This currently configures a non-tiled framebuffer on my SI system.

This design prevents drmModePageFlip from handling a framebuffer with a different tiling configuration.

Is this the intended architecture? i.e. All surfaces provided to drmModePageFlip should match the initial framebuffer layout, or should EVERGREEN_GRPH_CONTROL be updated on every page flip?