On Tue, Oct 29, 2019 at 03:32:41PM +0200, Jani Nikula wrote:
On Tue, 29 Oct 2019, Thierry Reding thierry.reding@gmail.com wrote:
From: Thierry Reding treding@nvidia.com
The current link status contains bytes 0x202 through 0x207, but we also want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c) so that the post-cursor adjustment can be queried during link training.
We don't currently use this in i915 (we probably should), so the impact here is that we'll just read more DPCD than before. I quickly perused i915, and this does not appear to directly break anything. I think the change is probably fine, but at the same time it freaks me out a bit...
If you don't mind, please resend this with Cc: intel-gfx@lists.freedesktop.org to have our CI crunch through it across a number of platforms. Would give me a warm fuzzy feeling. :)
With the caveat that I didn't look at any other drivers besides i915,
Reviewed-by: Jani Nikula jani.nikula@intel.com
Done, thanks.
Thierry