Hi Jagan, On Sun, Jul 04, 2021 at 02:32:29PM +0530, Jagan Teki wrote:
PMS_P offset value in existing driver is not compatible with i.MX8MM.
However the i.MX8M Mini Application Reference manual shows the PMS_P offset is the same in the driver, but the i.MX8MM downstream driver uses a different one.
So, handle the PMS_P offset via driver_data and use the offset value for i.MX8MM from the downstream driver.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
$subject and code speaks of PLL but the changelog says PMS. I think the changelog needs a small update here.
Sam
drivers/gpu/drm/bridge/samsung-dsim.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 54767cbf231c..0ed218f5eefc 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -184,7 +184,7 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) +#define DSIM_PLL_P(x, offset) ((x) << (offset)) #define DSIM_PLL_M(x) ((x) << 4) #define DSIM_PLL_S(x) ((x) << 1)
@@ -259,6 +259,7 @@ struct samsung_dsim_driver_data { unsigned int max_freq; unsigned int wait_for_reset; unsigned int num_bits_resol;
- unsigned int pll_p_offset; const unsigned int *reg_values; bool exynos_specific;
}; @@ -487,6 +488,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11,
- .pll_p_offset = 13, .reg_values = reg_values, .exynos_specific = true,
}; @@ -500,6 +502,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11,
- .pll_p_offset = 13, .reg_values = reg_values, .exynos_specific = true,
}; @@ -511,6 +514,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { .max_freq = 1000, .wait_for_reset = 1, .num_bits_resol = 11,
- .pll_p_offset = 13, .reg_values = reg_values, .exynos_specific = true,
}; @@ -523,6 +527,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 0, .num_bits_resol = 12,
- .pll_p_offset = 13, .reg_values = exynos5433_reg_values, .exynos_specific = true,
}; @@ -535,6 +540,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { .max_freq = 1500, .wait_for_reset = 1, .num_bits_resol = 12,
- .pll_p_offset = 13, .reg_values = exynos5422_reg_values, .exynos_specific = true,
}; @@ -547,6 +553,7 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { .max_freq = 2100, .wait_for_reset = 0, .num_bits_resol = 12,
- .pll_p_offset = 14, .reg_values = imx8mm_dsim_reg_values,
};
@@ -662,7 +669,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg);
- reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
DSIM_PLL_M(m) | DSIM_PLL_S(s);if (driver_data->has_freqband) { static const unsigned long freq_bands[] = {
-- 2.25.1