These will be used by a7xx, so move them to common code. A6XX_ prefix is kept because the generic ADRENO_ is already in use.
Signed-off-by: Jonathan Marek jonathan@marek.ca --- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 17 ----------------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++ 2 files changed, 6 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index 86e0a7c3fe6df..d117c1589f2af 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -36,23 +36,6 @@ struct a6xx_gpu {
#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)
-/* - * Given a register and a count, return a value to program into - * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len - * registers starting at _reg. - */ -#define A6XX_PROTECT_NORDWR(_reg, _len) \ - ((1 << 31) | \ - (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) - -/* - * Same as above, but allow reads over the range. For areas of mixed use (such - * as performance counters) this allows us to protect a much larger range with a - * single register - */ -#define A6XX_PROTECT_RDONLY(_reg, _len) \ - ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) - static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) { if(adreno_is_a630(gpu)) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 0490c5fbb7803..55c5433a4ea18 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -416,6 +416,10 @@ static inline uint32_t get_wptr(struct msm_ringbuffer *ring) ((1 << 30) | (1 << 29) | \ ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
+#define A6XX_PROTECT_NORDWR(_reg, _len) \ + ((1 << 31) | \ + (((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF)) + /* * Same as above, but allow reads over the range. For areas of mixed use (such * as performance counters) this allows us to protect a much larger range with a @@ -425,6 +429,8 @@ static inline uint32_t get_wptr(struct msm_ringbuffer *ring) ((1 << 29) \ ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
+#define A6XX_PROTECT_RDONLY(_reg, _len) \ + ((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \ readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \